[Commit-gnuradio] r7063 - usrp2/trunk/fpga/control_lib

[matt]

Author: matt
Date: 2007-12-03 14:32:34 -0700 (Mon, 03 Dec 2007)
New Revision: 7063

Modified:
   usrp2/trunk/fpga/control_lib/icache.v
Log:
changed ack logic to work when stb is gone.  Also fixed `defines namespace


Modified: usrp2/trunk/fpga/control_lib/icache.v
===================================================================
--- usrp2/trunk/fpga/control_lib/icache.v       2007-12-03 19:17:41 UTC (rev 
7062)
+++ usrp2/trunk/fpga/control_lib/icache.v       2007-12-03 21:32:34 UTC (rev 
7063)
@@ -76,15 +76,15 @@
      else 
        miss_d1 <= cache_miss;
 
-//`define NOCACHE
-//`define BASIC
-//`define FORWARDING_DP
-`define FORWARDING_SP
-//`define PREFETCH
+//`define IC_NOCACHE
+//`define IC_BASIC
+//`define IC_FORWARDING_DP
+`define IC_FORWARDING_SP
+//`define IC_PREFETCH
 
-`ifdef NOCACHE
+`ifdef IC_NOCACHE
    assign             iwb_dat_o = iram_dat_i;
-   assign             iwb_ack_o = iwb_stb_i & ~ack_d1;                
+   assign             iwb_ack_o = iwb_stb_i & (stb_d1 & ~ack_d1);
    assign             iram_adr_o = iwb_adr_i;
    assign             iram_en_o = 1'b1;
    assign             rd_line = 0;
@@ -93,7 +93,7 @@
    assign             store_in_cache = 0;
 `endif
    
-`ifdef BASIC    // Very basic, no forwarding, 2 wait states on miss
+`ifdef IC_BASIC    // Very basic, no forwarding, 2 wait states on miss
    assign             iwb_dat_o = data_out;
    assign             iwb_ack_o = iwb_stb_i & cache_hit;
    assign             iram_adr_o = iwb_adr_i;
@@ -104,9 +104,9 @@
    assign             store_in_cache = stb_d1 & miss_d1;
 `endif
    
-`ifdef FORWARDING_DP   // Simple forwarding, 1 wait state on miss, dual-port 
ram
+`ifdef IC_FORWARDING_DP   // Simple forwarding, 1 wait state on miss, 
dual-port ram
    assign             iwb_dat_o = cache_hit ? data_out : iram_dat_i;
-   assign             iwb_ack_o = iwb_stb_i & (cache_hit | ~ack_d1);
+   assign             iwb_ack_o = iwb_stb_i & (cache_hit | (stb_d1 & ~ack_d1));
    assign             iram_adr_o = iwb_adr_i;
    assign             iram_en_o = 1'b1;
    assign             rd_line = iwb_adr_i[CWIDTH+1:2];
@@ -115,9 +115,9 @@
    assign             store_in_cache = iwb_stb_i & stb_d1 & miss_d1 & ~ack_d1;
 `endif
 
-`ifdef FORWARDING_SP   // Simple forwarding, 1 wait state on miss, single-port 
ram
+`ifdef IC_FORWARDING_SP   // Simple forwarding, 1 wait state on miss, 
single-port ram
    assign             iwb_dat_o = cache_hit ? data_out : iram_dat_i;
-   assign             iwb_ack_o = iwb_stb_i & (cache_hit | ~ack_d1);
+   assign             iwb_ack_o = iwb_stb_i & (cache_hit | (stb_d1 & ~ack_d1));
    assign             iram_adr_o = iwb_adr_i;
    assign             iram_en_o = 1'b1;
    assign             rd_line = iwb_adr_i[CWIDTH+1:2];
@@ -126,7 +126,7 @@
    assign             store_in_cache = iwb_stb_i & stb_d1 & miss_d1 & ~ack_d1;
 `endif
 
-`ifdef PREFETCH   // Forwarding plus prefetch
+`ifdef IC_PREFETCH   // Forwarding plus prefetch
 
 `endif