[Commit-gnuradio] r7231 - usrp2/trunk/fpga/top/u2_fpga

[matt]

Author: matt
Date: 2007-12-19 13:51:16 -0700 (Wed, 19 Dec 2007)
New Revision: 7231

Modified:
   usrp2/trunk/fpga/top/u2_fpga/u2_fpga.ise
   usrp2/trunk/fpga/top/u2_fpga/u2_fpga_top.prj
   usrp2/trunk/fpga/top/u2_fpga/u2_fpga_top.v
Log:
connect aux_clk to already-connected phy_clk


Modified: usrp2/trunk/fpga/top/u2_fpga/u2_fpga.ise
===================================================================
(Binary files differ)

Modified: usrp2/trunk/fpga/top/u2_fpga/u2_fpga_top.prj
===================================================================
--- usrp2/trunk/fpga/top/u2_fpga/u2_fpga_top.prj        2007-12-19 19:53:54 UTC 
(rev 7230)
+++ usrp2/trunk/fpga/top/u2_fpga/u2_fpga_top.prj        2007-12-19 20:51:16 UTC 
(rev 7231)
@@ -2,7 +2,6 @@
 verilog work "../../control_lib/ram_2port.v"
 verilog work "../../opencores/uart16550/rtl/verilog/uart_tfifo.v"
 verilog work "../../opencores/uart16550/rtl/verilog/uart_rfifo.v"
-verilog work "../../eth/rtl/verilog/TECH/duram.v"
 verilog work "../../control_lib/shortfifo.v"
 verilog work "../../control_lib/longfifo.v"
 verilog work "../../sdr_lib/sign_extend.v"

Modified: usrp2/trunk/fpga/top/u2_fpga/u2_fpga_top.v
===================================================================
--- usrp2/trunk/fpga/top/u2_fpga/u2_fpga_top.v  2007-12-19 19:53:54 UTC (rev 
7230)
+++ usrp2/trunk/fpga/top/u2_fpga/u2_fpga_top.v  2007-12-19 20:51:16 UTC (rev 
7231)
@@ -149,7 +149,7 @@
    );
 
    // FPGA-specific pins connections
-   wire        aux_clk = RAM_CE1n;   // FIXME  Hacked on with Blue Wire
+   wire        aux_clk = PHY_CLK;
    wire        cpld_detached = RAM_A[14]; // FIXME  Hacked on with Blue Wire
 
    wire        clk_fpga, dsp_clk, clk_div, dcm_out, wb_clk, clock_ready;
@@ -213,13 +213,6 @@
    defparam DCM_INST.PHASE_SHIFT = 0;
    defparam DCM_INST.STARTUP_WAIT = "FALSE";
 
-   //BUFGMUX wbclk_BUFGMUX (.I0(aux_clk), 
-   //                       .I1(clk_div), 
-   //                       .S(clock_ready), 
-   //                       //.S(1'b0), 
-   //                       .O(wb_clk));
-
-   
    BUFG dspclk_BUFG (.I(dcm_out), .O(dsp_clk));
    BUFG wbclk_BUFG (.I(clk_div), .O(wb_clk));