[Commit-gnuradio] r7596 - in usrp2/trunk/fpga: opencores/simple_pic/rtl top/u2_basic

[matt]

Author: matt
Date: 2008-02-06 21:34:32 -0700 (Wed, 06 Feb 2008)
New Revision: 7596

Modified:
   usrp2/trunk/fpga/opencores/simple_pic/rtl/simple_pic.v
   usrp2/trunk/fpga/top/u2_basic/u2_basic.v
Log:
widen interrupts so we can have up to 32 of them


Modified: usrp2/trunk/fpga/opencores/simple_pic/rtl/simple_pic.v
===================================================================
--- usrp2/trunk/fpga/opencores/simple_pic/rtl/simple_pic.v      2008-02-07 
04:11:01 UTC (rev 7595)
+++ usrp2/trunk/fpga/opencores/simple_pic/rtl/simple_pic.v      2008-02-07 
04:34:32 UTC (rev 7596)
@@ -1,3 +1,6 @@
+
+// Modified by M. Ettus, 2008 for 32 bit width
+
 /////////////////////////////////////////////////////////////////////
 ////                                                             ////
 ////  OpenCores         Simple Programmable Interrupt Controller ////
@@ -31,30 +34,7 @@
 //// POSSIBILITY OF SUCH DAMAGE.                                 ////
 ////                                                             ////
 /////////////////////////////////////////////////////////////////////
-
-//  CVS Log
 //
-//  $Id: simple_pic.v,v 1.3 2002/12/24 10:26:51 rherveille Exp $
-//
-//  $Date: 2002/12/24 10:26:51 $
-//  $Revision: 1.3 $
-//  $Author: rherveille $
-//  $Locker:  $
-//  $State: Exp $
-//
-// Change History:
-//               $Log: simple_pic.v,v $
-//               Revision 1.3  2002/12/24 10:26:51  rherveille
-//               Fixed some typos in the documentation.
-//
-//               Revision 1.2  2002/12/22 16:11:03  rherveille
-//               *** empty log message ***
-//
-//
-
-
-
-//
 // This is a simple Programmable Interrupt Controller.
 // The number of interrupts is depending on the databus size.
 // There's one interrupt input per databit (i.e. 16 interrupts for a 16
@@ -110,17 +90,12 @@
 //
 
 
-// synopsys translate_off
-`include "timescale.v"
-// synopsys translate_on
-
 module simple_pic(
   clk_i, rst_i, cyc_i, stb_i, adr_i, we_i, dat_i, dat_o, ack_o, int_o,
   irq
 );
-
-  parameter is = 8;            // Number of interrupt sources
-
+   parameter is = 8;            // Number of interrupt sources
+   parameter dwidth = 32;
   //
   // Inputs & outputs
   //
@@ -132,8 +107,8 @@
   input         stb_i;         // strobe  (cycle and strobe are the same 
signal)
   input  [ 2:1] adr_i;         // address
   input         we_i;          // write enable
-  input  [ 7:0] dat_i;         // data output
-  output [ 7:0] dat_o;         // data input
+  input  [ dwidth-1:0] dat_i;         // data output
+  output [ dwidth-1:0] dat_o;         // data input
   output        ack_o;         // normal bus termination
 
   output        int_o;         // interrupt output
@@ -157,8 +132,8 @@
   // synopsys translate_off
   initial
   begin
-      if(is > 8)
-        $display("simple_pic: max. 8 interrupt sources supported.");
+      if(is > dwidth)
+        $display("simple_pic: max number of interrupts = data bus width.");
   end
   // synopsys translate_on
 
@@ -225,13 +200,13 @@
 
     //
     // generate dat_o
-    reg [7:0] dat_o;
+    reg [dwidth-1:0] dat_o;
     always @(posedge clk_i)
       case (adr_i) // synopsys full_case parallel_case
-        2'b00: dat_o <= #1 { {(8-is){1'b0}}, edgen};
-        2'b01: dat_o <= #1 { {(8-is){1'b0}}, pol};
-        2'b10: dat_o <= #1 { {(8-is){1'b0}}, mask};
-        2'b11: dat_o <= #1 { {(8-is){1'b0}}, pending};
+        2'b00: dat_o <= #1 { {(dwidth-is){1'b0}}, edgen};
+        2'b01: dat_o <= #1 { {(dwidth-is){1'b0}}, pol};
+        2'b10: dat_o <= #1 { {(dwidth-is){1'b0}}, mask};
+        2'b11: dat_o <= #1 { {(dwidth-is){1'b0}}, pending};
       endcase
 
    //

Modified: usrp2/trunk/fpga/top/u2_basic/u2_basic.v
===================================================================
--- usrp2/trunk/fpga/top/u2_basic/u2_basic.v    2008-02-07 04:11:01 UTC (rev 
7595)
+++ usrp2/trunk/fpga/top/u2_basic/u2_basic.v    2008-02-07 04:34:32 UTC (rev 
7596)
@@ -442,13 +442,11 @@
    // /////////////////////////////////////////////////////////////////////////
    // Interrupt Controller, Slave #8
 
-   //wire [7:0]         irq = 
{uart_int,overrun,underrun,PHY_INTn,i2c_int,spi_int,timer_int,buffer_int};
-   wire [7:0]   irq = 
{pps_int,overrun,underrun,PHY_INTn,i2c_int,spi_int,timer_int,buffer_int};
-   simple_pic simple_pic
+   wire [8:0]   
irq={uart_int,pps_int,overrun,underrun,PHY_INTn,i2c_int,spi_int,timer_int,buffer_int};
+   simple_pic #(.is(9),.dwidth(32)) simple_pic
      
(.clk_i(wb_clk),.rst_i(wb_rst),.cyc_i(s8_cyc),.stb_i(s8_stb),.adr_i(s8_adr[3:2]),
-      
.we_i(s8_we),.dat_i(s8_dat_o[7:0]),.dat_o(s8_dat_i[7:0]),.ack_o(s8_ack),.int_o(proc_int),
+      
.we_i(s8_we),.dat_i(s8_dat_o),.dat_o(s8_dat_i),.ack_o(s8_ack),.int_o(proc_int),
       .irq(irq) );
-   assign       s8_dat_i[31:8] = 0;
    assign       s8_err = 0;
    assign       s8_rty = 0;
         
@@ -588,19 +586,19 @@
 
    // Assign various commonly used debug buses.  Try to always have uart_tx_o 
on highest bit
    wire [31:0] debug_rx_1 = 
{uart_tx_o,GMII_TX_EN,strobe_rx,overrun,proc_int,buffer_int,timer_int,GMII_RX_DV,
-                            irq,
+                            irq[7:0],
                             GMII_RXD,
                             GMII_TXD};
    
    wire [31:0] debug_rx_2 = { 5'd0, s8_we, s8_stb, s8_ack, debug_rx[23:0] };
    
    wire [31:0] debug_time =  {uart_tx_o, 7'b0,
-                             irq,
+                             irq[7:0],
                              6'b0, GMII_RX_DV, GMII_TX_EN,
                              4'b0, exp_pps_in, exp_pps_out, pps_in, pps_int};
 
    wire [31:0] debug_irq =  {uart_tx_o, iwb_adr, iwb_ack,
-                            irq,
+                            irq[7:0],
                             proc_int,  7'b0 };