[Commit-gnuradio] r7795 - in gnuradio/branches/developers/jcorgan/iqb/usrp/fpga: sdr_lib toplevel/include toplevel/usrp_std

[jcorgan]

Author: jcorgan
Date: 2008-02-23 11:20:55 -0700 (Sat, 23 Feb 2008)
New Revision: 7795

Added:
   gnuradio/branches/developers/jcorgan/iqb/usrp/fpga/sdr_lib/iq_balancer.v
   
gnuradio/branches/developers/jcorgan/iqb/usrp/fpga/toplevel/include/common_config_1rxhb_1txiqb.vh
Modified:
   gnuradio/branches/developers/jcorgan/iqb/usrp/fpga/sdr_lib/cic_decim.v
   gnuradio/branches/developers/jcorgan/iqb/usrp/fpga/sdr_lib/cic_interp.v
   gnuradio/branches/developers/jcorgan/iqb/usrp/fpga/sdr_lib/clk_divider.v
   gnuradio/branches/developers/jcorgan/iqb/usrp/fpga/sdr_lib/cordic.v
   gnuradio/branches/developers/jcorgan/iqb/usrp/fpga/sdr_lib/cordic_stage.v
   gnuradio/branches/developers/jcorgan/iqb/usrp/fpga/sdr_lib/ddc.v
   gnuradio/branches/developers/jcorgan/iqb/usrp/fpga/sdr_lib/duc.v
   gnuradio/branches/developers/jcorgan/iqb/usrp/fpga/sdr_lib/phase_acc.v
   gnuradio/branches/developers/jcorgan/iqb/usrp/fpga/sdr_lib/tx_chain.v
   
gnuradio/branches/developers/jcorgan/iqb/usrp/fpga/toplevel/usrp_std/config.vh
   
gnuradio/branches/developers/jcorgan/iqb/usrp/fpga/toplevel/usrp_std/usrp_std.qsf
Log:
Wired in dummy balancer block.  Misc. cleanup on properties and FPGA project 
file.


Property changes on: 
gnuradio/branches/developers/jcorgan/iqb/usrp/fpga/sdr_lib/cic_decim.v
___________________________________________________________________
Name: svn:executable
   - *


Property changes on: 
gnuradio/branches/developers/jcorgan/iqb/usrp/fpga/sdr_lib/cic_interp.v
___________________________________________________________________
Name: svn:executable
   - *


Property changes on: 
gnuradio/branches/developers/jcorgan/iqb/usrp/fpga/sdr_lib/clk_divider.v
___________________________________________________________________
Name: svn:executable
   - *


Property changes on: 
gnuradio/branches/developers/jcorgan/iqb/usrp/fpga/sdr_lib/cordic.v
___________________________________________________________________
Name: svn:executable
   - *


Property changes on: 
gnuradio/branches/developers/jcorgan/iqb/usrp/fpga/sdr_lib/cordic_stage.v
___________________________________________________________________
Name: svn:executable
   - *


Property changes on: 
gnuradio/branches/developers/jcorgan/iqb/usrp/fpga/sdr_lib/ddc.v
___________________________________________________________________
Name: svn:executable
   - *


Property changes on: 
gnuradio/branches/developers/jcorgan/iqb/usrp/fpga/sdr_lib/duc.v
___________________________________________________________________
Name: svn:executable
   - *

Added: gnuradio/branches/developers/jcorgan/iqb/usrp/fpga/sdr_lib/iq_balancer.v
===================================================================
--- gnuradio/branches/developers/jcorgan/iqb/usrp/fpga/sdr_lib/iq_balancer.v    
                        (rev 0)
+++ gnuradio/branches/developers/jcorgan/iqb/usrp/fpga/sdr_lib/iq_balancer.v    
2008-02-23 18:20:55 UTC (rev 7795)
@@ -0,0 +1,36 @@
+// -*- verilog -*-
+//
+//  USRP - Universal Software Radio Peripheral
+//
+//  Copyright (C) 2007 Corgan Enterprises LLC
+//
+//  This program is free software; you can redistribute it and/or modify
+//  it under the terms of the GNU General Public License as published by
+//  the Free Software Foundation; either version 2 of the License, or
+//  (at your option) any later version.
+//
+//  This program is distributed in the hope that it will be useful,
+//  but WITHOUT ANY WARRANTY; without even the implied warranty of
+//  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+//  GNU General Public License for more details.
+//
+//  You should have received a copy of the GNU General Public License
+//  along with this program; if not, write to the Free Software
+//  Foundation, Inc., 51 Franklin Street, Boston, MA  02110-1301  USA
+//
+
+module iq_balancer(input clock, 
+                  input enable, 
+                  input reset,
+                  input signed [15:0] i_in, 
+                  input signed [15:0] q_in,
+                  output signed [15:0] i_out, 
+                  output signed [15:0] q_out,
+                  input wire [6:0] serial_addr, 
+                  input wire [31:0] serial_data, 
+                  input serial_strobe);
+
+    assign i_out = i_in;
+    assign q_out = q_in;
+
+endmodule // iq_balancer


Property changes on: 
gnuradio/branches/developers/jcorgan/iqb/usrp/fpga/sdr_lib/phase_acc.v
___________________________________________________________________
Name: svn:executable
   - *

Modified: gnuradio/branches/developers/jcorgan/iqb/usrp/fpga/sdr_lib/tx_chain.v
===================================================================
--- gnuradio/branches/developers/jcorgan/iqb/usrp/fpga/sdr_lib/tx_chain.v       
2008-02-23 17:58:24 UTC (rev 7794)
+++ gnuradio/branches/developers/jcorgan/iqb/usrp/fpga/sdr_lib/tx_chain.v       
2008-02-23 18:20:55 UTC (rev 7795)
@@ -34,7 +34,8 @@
    );
 
    wire [15:0] bb_i, bb_q;
-
+   wire [15:0] bb_i_bal, bb_q_bal;
+   
    cic_interp cic_interp_i
      ( .clock(clock),.reset(reset),.enable(enable),
        
.rate(interp_rate),.strobe_in(interpolator_strobe),.strobe_out(sample_strobe),
@@ -47,8 +48,8 @@
    
 `define NOCORDIC_TX
 `ifdef NOCORDIC_TX
-   assign      i_out = bb_i;
-   assign      q_out = bb_q;
+   assign      bb_i_bal = bb_i;
+   assign      bb_q_bal = bb_q;
 `else
    wire [31:0] phase;
 
@@ -59,7 +60,20 @@
    cordic tx_cordic_0
      ( .clock(clock),.reset(reset),.enable(sample_strobe), 
        .xi(bb_i),.yi(bb_q),.zi(phase[31:16]),
-       .xo(i_out),.yo(q_out),.zo() );
+       .xo(bb_i_bal),.yo(bb_q_bal),.zo() );
 `endif
 
+`ifdef TX_IQB_ON
+   iq_balancer tx_iq_balancer(.clock(clock),
+                             .enable(enable),
+                             .reset(reset),
+                             .i_in(bb_i_bal),
+                             .q_in(bb_q_bal),
+                             .i_out(i_out),
+                             .q_out(q_out) );
+`else
+    assign i_out = bb_i_bal;
+    assign q_out = bb_q_bal;
+`endif
+
 endmodule // tx_chain

Added: 
gnuradio/branches/developers/jcorgan/iqb/usrp/fpga/toplevel/include/common_config_1rxhb_1txiqb.vh
===================================================================
--- 
gnuradio/branches/developers/jcorgan/iqb/usrp/fpga/toplevel/include/common_config_1rxhb_1txiqb.vh
                           (rev 0)
+++ 
gnuradio/branches/developers/jcorgan/iqb/usrp/fpga/toplevel/include/common_config_1rxhb_1txiqb.vh
   2008-02-23 18:20:55 UTC (rev 7795)
@@ -0,0 +1,66 @@
+// -*- verilog -*-
+//
+//  USRP - Universal Software Radio Peripheral
+//
+//  Copyright (C) 2006 Matt Ettus
+//  Copyright (C) 2008 Corgan Enterprises LLC
+//
+//  This program is free software; you can redistribute it and/or modify
+//  it under the terms of the GNU General Public License as published by
+//  the Free Software Foundation; either version 2 of the License, or
+//  (at your option) any later version.
+//
+//  This program is distributed in the hope that it will be useful,
+//  but WITHOUT ANY WARRANTY; without even the implied warranty of
+//  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+//  GNU General Public License for more details.
+//
+//  You should have received a copy of the GNU General Public License
+//  along with this program; if not, write to the Free Software
+//  Foundation, Inc., 51 Franklin Street, Boston, MA  02110-1301  USA
+//
+
+// ------------------------------------------------------------
+// If TX_ON is not defined, there is *no* transmit circuitry built
+  `define TX_ON
+
+// ------------------------------------------------------------
+// Define 1 and only one of TX_SINGLE, TX_DUAL and TX_QUAD
+// to respectively enable 1, 2 or 4 transmit channels.
+// [Please note that only TX_SINGLE and TX_DUAL are currently valid]
+  `define TX_SINGLE
+//`define TX_DUAL
+//`define TX_QUAD
+
+// ------------------------------------------------------------
+// Define TX_HB_ON to enable the transmit halfband filter
+// [Not implemented]
+//`define TX_HB_ON
+
+// ------------------------------------------------------------
+// Define TX_IQB_ON to enable the transmit halfband filter
+  `define TX_IQB_ON
+
+// ------------------------------------------------------------
+// IF RX_ON is not defined, there is *no* receive circuitry built
+  `define RX_ON
+
+// ------------------------------------------------------------
+// Define 1 and only one of RX_SINGLE, RX_DUAL and RX_QUAD
+// to respectively define 1, 2 or 4 receive channels.
+
+  `define RX_SINGLE
+//`define RX_DUAL
+//`define RX_QUAD
+
+// ------------------------------------------------------------
+// Define RX_HB_ON to enable the receive halfband filter
+  `define RX_HB_ON
+
+// ------------------------------------------------------------
+// Define RX_NCO_ON to enable the receive Numerical Controlled Osc
+  `define RX_NCO_ON
+
+// ------------------------------------------------------------
+// Define RX_CIC_ON to enable the receive Cascaded Integrator Comb filter
+  `define RX_CIC_ON

Modified: 
gnuradio/branches/developers/jcorgan/iqb/usrp/fpga/toplevel/usrp_std/config.vh
===================================================================
--- 
gnuradio/branches/developers/jcorgan/iqb/usrp/fpga/toplevel/usrp_std/config.vh  
    2008-02-23 17:58:24 UTC (rev 7794)
+++ 
gnuradio/branches/developers/jcorgan/iqb/usrp/fpga/toplevel/usrp_std/config.vh  
    2008-02-23 18:20:55 UTC (rev 7795)
@@ -34,7 +34,7 @@
 //`include "../include/common_config_1rxhb_1tx.vh"
 
 // Uncomment this for 2 rx channels (w/ halfband) & 2 transmit channels
-  `include "../include/common_config_2rxhb_2tx.vh"
+//`include "../include/common_config_2rxhb_2tx.vh"
 
 // Uncomment this for 4 rx channels (w/o halfband) & 0 transmit channels
 //`include "../include/common_config_4rx_0tx.vh"
@@ -47,6 +47,9 @@
 
 // Add other "known to fit" configurations here...
 
+// Uncomment this for 1 rx channel (w/ halfband) & 1 transmit channel (w/ IQ 
balancer)
+`include "../include/common_config_1rxhb_1txiqb.vh"
+
 // ====================================================================
 //  Now include the common footer
 // ====================================================================

Modified: 
gnuradio/branches/developers/jcorgan/iqb/usrp/fpga/toplevel/usrp_std/usrp_std.qsf
===================================================================
--- 
gnuradio/branches/developers/jcorgan/iqb/usrp/fpga/toplevel/usrp_std/usrp_std.qsf
   2008-02-23 17:58:24 UTC (rev 7794)
+++ 
gnuradio/branches/developers/jcorgan/iqb/usrp/fpga/toplevel/usrp_std/usrp_std.qsf
   2008-02-23 18:20:55 UTC (rev 7795)
@@ -370,40 +370,41 @@
 
 set_instance_assignment -name PARTITION_HIERARCHY no_file_for_top_partition 
-to | -section_id Top
 set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
+set_global_assignment -name VERILOG_FILE ../../megacells/bustri.v
+set_global_assignment -name VERILOG_FILE ../../megacells/clk_doubler.v
+set_global_assignment -name VERILOG_FILE ../../megacells/fifo_2k.v
 set_global_assignment -name VERILOG_FILE ../../megacells/fifo_4k_18.v
+set_global_assignment -name VERILOG_FILE ../../megacells/fifo_4k.v
+set_global_assignment -name VERILOG_FILE ../../sdr_lib/adc_interface.v
 set_global_assignment -name VERILOG_FILE ../../sdr_lib/atr_delay.v
+set_global_assignment -name VERILOG_FILE ../../sdr_lib/bidir_reg.v
+set_global_assignment -name VERILOG_FILE ../../sdr_lib/cic_decim.v
 set_global_assignment -name VERILOG_FILE ../../sdr_lib/cic_dec_shifter.v
-set_global_assignment -name VERILOG_FILE ../../sdr_lib/rssi.v
-set_global_assignment -name VERILOG_FILE ../../sdr_lib/ram16.v
-set_global_assignment -name VERILOG_FILE ../../megacells/fifo_4k.v
+set_global_assignment -name VERILOG_FILE ../../sdr_lib/cic_interp.v
+set_global_assignment -name VERILOG_FILE ../../sdr_lib/cic_int_shifter.v
+set_global_assignment -name VERILOG_FILE ../../sdr_lib/clk_divider.v
+set_global_assignment -name VERILOG_FILE ../../sdr_lib/cordic_stage.v
+set_global_assignment -name VERILOG_FILE ../../sdr_lib/cordic.v
+set_global_assignment -name VERILOG_FILE ../../sdr_lib/gen_sync.v
 set_global_assignment -name VERILOG_FILE ../../sdr_lib/hb/acc.v
-set_global_assignment -name VERILOG_FILE ../../sdr_lib/hb/mult.v
-set_global_assignment -name VERILOG_FILE ../../sdr_lib/hb/ram16_2sum.v
 set_global_assignment -name VERILOG_FILE ../../sdr_lib/hb/coeff_rom.v
 set_global_assignment -name VERILOG_FILE ../../sdr_lib/hb/halfband_decim.v
 set_global_assignment -name VERILOG_FILE ../../sdr_lib/hb/mac.v
-set_global_assignment -name VERILOG_FILE ../../sdr_lib/tx_chain.v
-set_global_assignment -name VERILOG_FILE ../../sdr_lib/rx_dcoffset.v
-set_global_assignment -name VERILOG_FILE ../../sdr_lib/adc_interface.v
+set_global_assignment -name VERILOG_FILE ../../sdr_lib/hb/mult.v
+set_global_assignment -name VERILOG_FILE ../../sdr_lib/hb/ram16_2sum.v
 set_global_assignment -name VERILOG_FILE ../../sdr_lib/io_pins.v
-set_global_assignment -name VERILOG_FILE ../../sdr_lib/setting_reg.v
-set_global_assignment -name VERILOG_FILE ../../sdr_lib/bidir_reg.v
-set_global_assignment -name VERILOG_FILE ../../sdr_lib/cic_int_shifter.v
-set_global_assignment -name VERILOG_FILE ../../megacells/clk_doubler.v
-set_global_assignment -name VERILOG_FILE ../../sdr_lib/rx_chain.v
-set_global_assignment -name VERILOG_FILE ../../sdr_lib/gen_sync.v
+set_global_assignment -name VERILOG_FILE ../../sdr_lib/iq_balancer.v
 set_global_assignment -name VERILOG_FILE ../../sdr_lib/master_control.v
-set_global_assignment -name VERILOG_FILE ../../megacells/fifo_2k.v
-set_global_assignment -name VERILOG_FILE ../../megacells/bustri.v
+set_global_assignment -name VERILOG_FILE ../../sdr_lib/phase_acc.v
+set_global_assignment -name VERILOG_FILE ../../sdr_lib/ram16.v
+set_global_assignment -name VERILOG_FILE ../../sdr_lib/rssi.v
 set_global_assignment -name VERILOG_FILE ../../sdr_lib/rx_buffer.v
+set_global_assignment -name VERILOG_FILE ../../sdr_lib/rx_chain.v
+set_global_assignment -name VERILOG_FILE ../../sdr_lib/rx_dcoffset.v
+set_global_assignment -name VERILOG_FILE ../../sdr_lib/serial_io.v
+set_global_assignment -name VERILOG_FILE ../../sdr_lib/setting_reg.v
+set_global_assignment -name VERILOG_FILE ../../sdr_lib/sign_extend.v
+set_global_assignment -name VERILOG_FILE ../../sdr_lib/strobe_gen.v
 set_global_assignment -name VERILOG_FILE ../../sdr_lib/tx_buffer.v
-set_global_assignment -name VERILOG_FILE ../../sdr_lib/phase_acc.v
-set_global_assignment -name VERILOG_FILE ../../sdr_lib/cic_interp.v
-set_global_assignment -name VERILOG_FILE ../../sdr_lib/cic_decim.v
-set_global_assignment -name VERILOG_FILE ../../sdr_lib/cordic_stage.v
-set_global_assignment -name VERILOG_FILE ../../sdr_lib/cordic.v
+set_global_assignment -name VERILOG_FILE ../../sdr_lib/tx_chain.v
 set_global_assignment -name VERILOG_FILE usrp_std.v
-set_global_assignment -name VERILOG_FILE ../../sdr_lib/clk_divider.v
-set_global_assignment -name VERILOG_FILE ../../sdr_lib/serial_io.v
-set_global_assignment -name VERILOG_FILE ../../sdr_lib/strobe_gen.v
-set_global_assignment -name VERILOG_FILE ../../sdr_lib/sign_extend.v
\ No newline at end of file