[Commit-gnuradio] r7798 - in gnuradio/branches/developers/jcorgan/iqb/usrp: firmware/include fpga/sdr_lib

[jcorgan]

Author: jcorgan
Date: 2008-02-23 12:54:22 -0700 (Sat, 23 Feb 2008)
New Revision: 7798

Modified:
   
gnuradio/branches/developers/jcorgan/iqb/usrp/firmware/include/fpga_regs_standard.h
   
gnuradio/branches/developers/jcorgan/iqb/usrp/firmware/include/fpga_regs_standard.v
   gnuradio/branches/developers/jcorgan/iqb/usrp/fpga/sdr_lib/iq_balancer.v
Log:
Added DC offset compensation.

Modified: 
gnuradio/branches/developers/jcorgan/iqb/usrp/firmware/include/fpga_regs_standard.h
===================================================================
--- 
gnuradio/branches/developers/jcorgan/iqb/usrp/firmware/include/fpga_regs_standard.h
 2008-02-23 19:24:35 UTC (rev 7797)
+++ 
gnuradio/branches/developers/jcorgan/iqb/usrp/firmware/include/fpga_regs_standard.h
 2008-02-23 19:54:22 UTC (rev 7798)
@@ -182,10 +182,27 @@
 // 12 takes a bit more work, since we need to know packet alignment.
 
 // ------------------------------------------------------------------------
-// Transmitter I/Q balancer base register
+// Tx I/Q balancer base register
 #define FR_TX_IQ_BALANCER_BASE 50
 
 // ------------------------------------------------------------------------
+// Tx I/Q balancer offset adjustment
+//
+//    3                   2                   1                       
+//  1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+// +-------------------------------+-------------------------------+
+// |     I channel DC offset       |        Q channel DC offset    |
+// +-------------------------------+-------------------------------+
+//
+// Each of these values is added to the corresponding value as the
+// final step in the transmit DSP pipeline.
+//
+#define FR_TX_IQ_OFFSET_ADJ     50
+
+#define FR_TX_IQ_MAG_ADJ        51
+#define FR_TX_IQ_PHASE_ADJ      52
+
+// ------------------------------------------------------------------------
 // FIXME register numbers 53 to 63 are available
 
 // ------------------------------------------------------------------------

Modified: 
gnuradio/branches/developers/jcorgan/iqb/usrp/firmware/include/fpga_regs_standard.v
===================================================================
--- 
gnuradio/branches/developers/jcorgan/iqb/usrp/firmware/include/fpga_regs_standard.v
 2008-02-23 19:24:35 UTC (rev 7797)
+++ 
gnuradio/branches/developers/jcorgan/iqb/usrp/firmware/include/fpga_regs_standard.v
 2008-02-23 19:54:22 UTC (rev 7798)
@@ -154,10 +154,27 @@
 // 12 takes a bit more work, since we need to know packet alignment.
 
 // ------------------------------------------------------------------------
-// Transmitter I/Q balancer base register
+// Tx I/Q balancer base register
 `define FR_TX_IQ_BALANCER_BASE    7'd50
 
 // ------------------------------------------------------------------------
+// Tx I/Q balancer offset adjustment
+//
+//    3                   2                   1                       
+//  1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+// +-------------------------------+-------------------------------+
+// |     I channel DC offset       |        Q channel DC offset    |
+// +-------------------------------+-------------------------------+
+//
+// Each of these values is added to the corresponding value as the
+// final step in the transmit DSP pipeline.
+//
+`define FR_TX_IQ_OFFSET_ADJ       7'd50
+
+`define FR_TX_IQ_MAG_ADJ          7'd51
+`define FR_TX_IQ_PHASE_ADJ        7'd52
+
+// ------------------------------------------------------------------------
 // FIXME register numbers 53 to 63 are available
 
 // ------------------------------------------------------------------------

Modified: 
gnuradio/branches/developers/jcorgan/iqb/usrp/fpga/sdr_lib/iq_balancer.v
===================================================================
--- gnuradio/branches/developers/jcorgan/iqb/usrp/fpga/sdr_lib/iq_balancer.v    
2008-02-23 19:24:35 UTC (rev 7797)
+++ gnuradio/branches/developers/jcorgan/iqb/usrp/fpga/sdr_lib/iq_balancer.v    
2008-02-23 19:54:22 UTC (rev 7798)
@@ -36,11 +36,11 @@
    localparam MAG_ADDR    = REGBASE + 1;
    localparam PHASE_ADDR  = REGBASE + 2;
 
-   wire [15:0] i_offset;
-   wire [15:0] q_offset;
-   wire [15:0] i_mag;
-   wire [15:0] i_phase_k;
-   wire [15:0] q_phase_k;
+   wire [15:0] i_offset_adj;
+   wire [15:0] q_offset_adj;
+   wire [15:0] i_mag_adj;
+   wire [15:0] i_phase_adj;
+   wire [15:0] q_phase_adj;
    
    setting_reg #(OFFSET_ADDR) sr_offset
      (.clock(clock),
@@ -48,7 +48,7 @@
       .strobe(serial_strobe),
       .addr(serial_addr),
       .in(serial_data),
-      .out({i_offset,q_offset}) );
+      .out({i_offset_adj,q_offset_adj}) );
 
    setting_reg #(MAG_ADDR) sr_mag
      (.clock(clock),
@@ -56,7 +56,7 @@
       .strobe(serial_strobe),
       .addr(serial_addr),
       .in(serial_data),
-      .out(i_mag) );
+      .out(i_mag_adj) );
 
    setting_reg #(PHASE_ADDR) sr_phase
      (.clock(clock),
@@ -64,9 +64,13 @@
       .strobe(serial_strobe),
       .addr(serial_addr),
       .in(serial_data),
-      .out({i_phase_k,q_phase_k}) );
+      .out({i_phase_adj,q_phase_adj}) );
 
-   assign i_out = i_in;
-   assign q_out = q_in;
+   // Add in DC offset balance
+   wire [15:0] i_offset_bal = i_in + i_offset_adj;
+   wire [15:0] q_offset_bal = q_in + q_offset_adj;
+   
+   assign i_out = i_offset_bal;
+   assign q_out = q_offset_bal;
 
 endmodule // iq_balancer