[Commit-gnuradio] r7818 - usrp2/trunk/fpga/top/u2_fpga

[matt]

Author: matt
Date: 2008-02-24 12:08:20 -0700 (Sun, 24 Feb 2008)
New Revision: 7818

Modified:
   usrp2/trunk/fpga/top/u2_fpga/u2_fpga_top.v
Log:
register the serdes outputs in the iobuffer flops


Modified: usrp2/trunk/fpga/top/u2_fpga/u2_fpga_top.v
===================================================================
--- usrp2/trunk/fpga/top/u2_fpga/u2_fpga_top.v  2008-02-24 19:07:53 UTC (rev 
7817)
+++ usrp2/trunk/fpga/top/u2_fpga/u2_fpga_top.v  2008-02-24 19:08:20 UTC (rev 
7818)
@@ -57,9 +57,9 @@
    output ser_rx_en,
    
    output ser_tx_clk,
-   output [15:0] ser_t,
-   output ser_tklsb,
-   output ser_tkmsb,
+   output reg [15:0] ser_t,
+   output reg ser_tklsb,
+   output reg ser_tkmsb,
 
    input ser_rx_clk,
    input [15:0] ser_r,
@@ -251,7 +251,7 @@
        GMII_TXD <= GMII_TXD_unreg;
      end
 
-   OFDDRRSE OFDDRRSE_inst 
+   OFDDRRSE OFDDRRSE_gmii_inst 
      (.Q(GMII_GTX_CLK),      // Data output (connect directly to top-level 
port)
       .C0(GMII_GTX_CLK_int),    // 0 degree clock input
       .C1(~GMII_GTX_CLK_int),    // 180 degree clock input
@@ -262,6 +262,31 @@
       .S(0)       // Synchronous preset input
       );
    
+   wire ser_tklsb_unreg, ser_tkmsb_unreg;
+   wire [15:0] ser_t_unreg;
+   wire        ser_tx_clk_int;
+   
+   always @(posedge ser_tx_clk_int)
+     begin
+       ser_tklsb <= ser_tklsb_unreg;
+       ser_tkmsb <= ser_tkmsb_unreg;
+       ser_t <= ser_t_unreg;
+     end
+
+   assign ser_tx_clk = clk_fpga;
+   
+   /*
+   OFDDRRSE OFDDRRSE_serdes_inst 
+     (.Q(ser_tx_clk),      // Data output (connect directly to top-level port)
+      .C0(ser_tx_clk_int),    // 0 degree clock input
+      .C1(~ser_tx_clk_int),    // 180 degree clock input
+      .CE(1),    // Clock enable input
+      .D0(0),    // Posedge data input
+      .D1(1),    // Negedge data input
+      .R(0),      // Synchronous reset input
+      .S(0)       // Synchronous preset input
+      );
+   */
    u2_basic u2_basic(.dsp_clk           (dsp_clk),
                     .wb_clk            (wb_clk),
                     .clock_ready       (clock_ready),
@@ -293,10 +318,10 @@
                     .ser_prbsen        (ser_prbsen),
                     .ser_loopen        (ser_loopen),
                     .ser_rx_en         (ser_rx_en),
-                    .ser_tx_clk        (ser_tx_clk),
-                    .ser_t             (ser_t[15:0]),
-                    .ser_tklsb         (ser_tklsb),
-                    .ser_tkmsb         (ser_tkmsb),
+                    .ser_tx_clk        (ser_tx_clk_int),
+                    .ser_t             (ser_t_unreg[15:0]),
+                    .ser_tklsb         (ser_tklsb_unreg),
+                    .ser_tkmsb         (ser_tkmsb_unreg),
                     .ser_rx_clk        (ser_rx_clk),
                     .ser_r             (ser_r[15:0]),
                     .ser_rklsb         (ser_rklsb),