[Commit-gnuradio] r7961 - in usrp2/trunk/fpga/top: u2_basic u2_fpga

[matt]

Author: matt
Date: 2008-03-07 16:49:08 -0700 (Fri, 07 Mar 2008)
New Revision: 7961

Modified:
   usrp2/trunk/fpga/top/u2_basic/u2_basic.v
   usrp2/trunk/fpga/top/u2_fpga/u2_fpga.ise
   usrp2/trunk/fpga/top/u2_fpga/u2_fpga_top.v
Log:
flop serdes where it comes into the chip, plus debug pins


Modified: usrp2/trunk/fpga/top/u2_basic/u2_basic.v
===================================================================
--- usrp2/trunk/fpga/top/u2_basic/u2_basic.v    2008-03-07 20:55:59 UTC (rev 
7960)
+++ usrp2/trunk/fpga/top/u2_basic/u2_basic.v    2008-03-07 23:49:08 UTC (rev 
7961)
@@ -146,7 +146,7 @@
    wire [31:0]         debug_gpio_0, debug_gpio_1;
    wire [31:0]         atr_lines;
 
-   wire [31:0]         debug_rx, debug_mac0, debug_mac1, debug_txc, 
debug_serdes0, debug_serdes1;
+   wire [31:0]         debug_rx, debug_mac0, debug_mac1, debug_txc, 
debug_serdes0, debug_serdes1, debug_serdes2;
    // 
///////////////////////////////////////////////////////////////////////////////////////////////
    // Wishbone Single Master INTERCON
    parameter   dw = 32;  // Data bus width
@@ -567,7 +567,7 @@
       
.ser_rx_clk(ser_rx_clk),.ser_r(ser_r),.ser_rklsb(ser_rklsb),.ser_rkmsb(ser_rkmsb),
       
.wr_dat_o(wr0_dat),.wr_write_o(wr0_write),.wr_done_o(wr0_done),.wr_error_o(wr0_error),
       .wr_ready_i(wr0_ready),.wr_full_i(wr0_full),
-      .debug(debug_serdes0) );
+      .debug(debug_serdes2) );
 
    // 
///////////////////////////////////////////////////////////////////////////////////
    // External RAM Interface
@@ -608,30 +608,33 @@
                {8'd0},
                {8'd0},
                
{GMII_TX_EN,GMII_RX_DV,Rx_mac_empty,Rx_mac_rd,Rx_mac_err,Rx_mac_sop,Rx_mac_eop,wr2_full}
 };
-   /*
-   assign      debug_serdes0 = { { rd0_dat },
+
+   assign      debug_serdes0 = { { rd0_dat[7:0] },
                                 { ser_tx_clk, ser_tkmsb, ser_tklsb, rd0_sop, 
rd0_eop, rd0_read, rd0_error, rd0_done },
                                 { ser_t[15:8] },
                                 { ser_t[7:0] } };
-   
+
    assign      debug_serdes1 = { 
{uart_tx_o,proc_int,underrun,buffer_int,wr0_ready,wr0_error,wr0_done,wr0_write},
                                 { 1'b0, ser_rx_clk, ser_rkmsb, ser_rklsb, 
ser_enable, ser_prbsen, ser_loopen, ser_rx_en },
                                 { ser_r[15:8] },
                                 { ser_r[7:0] } };
-   */
+
    
    // Choose actual debug buses
-   assign      debug = debug_mac0;
+   assign      debug = debug_serdes0;
    assign      debug_clk[0] = wb_clk;
    assign      debug_clk[1] = dsp_clk; 
    assign      debug_gpio_0 = 32'd0;  // Not used b/c of ATR
-/*
+
+   /*
    assign      debug_gpio_1 = {uart_tx_o,7'd0,
                               3'd0,rd1_sop,rd1_eop,rd1_read,rd1_done,rd1_error,
                               debug_txc[15:0]};
    assign      debug_gpio_1 = debug_rx;
+    */
+   
    assign      debug_gpio_1 = debug_serdes1;
- */
-   assign      debug_gpio_1 = debug_eth;
+
+ //assign      debug_gpio_1 = debug_eth;
       
 endmodule // u2_basic

Modified: usrp2/trunk/fpga/top/u2_fpga/u2_fpga.ise
===================================================================
(Binary files differ)

Modified: usrp2/trunk/fpga/top/u2_fpga/u2_fpga_top.v
===================================================================
--- usrp2/trunk/fpga/top/u2_fpga/u2_fpga_top.v  2008-03-07 20:55:59 UTC (rev 
7960)
+++ usrp2/trunk/fpga/top/u2_fpga/u2_fpga_top.v  2008-03-07 23:49:08 UTC (rev 
7961)
@@ -274,6 +274,16 @@
      end
 
    assign ser_tx_clk = clk_fpga;
+
+   reg [15:0] ser_r_int;
+   reg               ser_rklsb_int, ser_rkmsb_int;
+
+   always @(posedge ser_rx_clk)
+     begin
+       ser_r_int <= ser_r;
+       ser_rklsb_int <= ser_rklsb;
+       ser_rkmsb_int <= ser_rkmsb_int;
+     end
    
    /*
    OFDDRRSE OFDDRRSE_serdes_inst 
@@ -323,9 +333,9 @@
                     .ser_tklsb         (ser_tklsb_unreg),
                     .ser_tkmsb         (ser_tkmsb_unreg),
                     .ser_rx_clk        (ser_rx_clk),
-                    .ser_r             (ser_r[15:0]),
-                    .ser_rklsb         (ser_rklsb),
-                    .ser_rkmsb         (ser_rkmsb),
+                    .ser_r             (ser_r_int[15:0]),
+                    .ser_rklsb         (ser_rklsb_int),
+                    .ser_rkmsb         (ser_rkmsb_int),
                     .cpld_start        (cpld_start),
                     .cpld_mode         (cpld_mode),
                     .cpld_done         (cpld_done),