[Commit-gnuradio] r8007 - usrp2/trunk/fpga/serdes

[matt]

Author: matt
Date: 2008-03-12 14:26:37 -0600 (Wed, 12 Mar 2008)
New Revision: 8007

Modified:
   usrp2/trunk/fpga/serdes/serdes.v
   usrp2/trunk/fpga/serdes/serdes_fc_rx.v
   usrp2/trunk/fpga/serdes/serdes_fc_tx.v
Log:
fixed serdes clocking, plus corrected meanings of xon/xoff


Modified: usrp2/trunk/fpga/serdes/serdes.v
===================================================================
--- usrp2/trunk/fpga/serdes/serdes.v    2008-03-12 20:21:12 UTC (rev 8006)
+++ usrp2/trunk/fpga/serdes/serdes.v    2008-03-12 20:26:37 UTC (rev 8007)
@@ -37,7 +37,8 @@
 
    serdes_fc_tx serdes_fc_tx
      (.clk(clk),.rst(rst),
-      .xon_rcvd(xon_rcvd),.xoff_rcvd(xoff_rcvd),.inhibit_tx(inhibit_tx) );
+      .ser_rx_clk(ser_rx_clk),.xon_rcvd(xon_rcvd),.xoff_rcvd(xoff_rcvd),
+      .inhibit_tx(inhibit_tx) );
 
    serdes_fc_rx #(.LWMARK(32),.HWMARK(128)) serdes_fc_rx
      (.clk(clk),.rst(rst),

Modified: usrp2/trunk/fpga/serdes/serdes_fc_rx.v
===================================================================
--- usrp2/trunk/fpga/serdes/serdes_fc_rx.v      2008-03-12 20:21:12 UTC (rev 
8006)
+++ usrp2/trunk/fpga/serdes/serdes_fc_rx.v      2008-03-12 20:26:37 UTC (rev 
8007)
@@ -2,7 +2,7 @@
 
 module serdes_fc_rx
   #(parameter LWMARK = 64,
-    parameter HWMARK = 160)
+    parameter HWMARK = 320)
     (input clk, input rst,
      input [15:0] fifo_space, 
      output reg send_xon,
@@ -26,7 +26,7 @@
          if(countdown == 0)
            if(fifo_space < LWMARK)
              begin
-                send_xon_int <= 1;
+                send_xoff_int <= 1;
                 countdown <= 240;
              end
            else
@@ -34,7 +34,7 @@
          else
            if(fifo_space > HWMARK)
              begin
-                send_xoff_int <= 1;
+                send_xon_int <= 1;
                 countdown <= 0;
              end
            else

Modified: usrp2/trunk/fpga/serdes/serdes_fc_tx.v
===================================================================
--- usrp2/trunk/fpga/serdes/serdes_fc_tx.v      2008-03-12 20:21:12 UTC (rev 
8006)
+++ usrp2/trunk/fpga/serdes/serdes_fc_tx.v      2008-03-12 20:26:37 UTC (rev 
8007)
@@ -2,20 +2,43 @@
 
 module serdes_fc_tx
   (input clk, input rst,
-   input xon_rcvd, input xoff_rcvd, output inhibit_tx);
+   input ser_rx_clk, input xon_rcvd, input xoff_rcvd, output reg inhibit_tx);
 
-   reg [15:0] state;
+   // XOFF means stop sending, XON means start sending
+   
+   reg          xon_d1, xon_d2, xoff_d1, xoff_d2;
+   reg          xon_ret, xon_ret_d1, xoff_ret, xoff_ret_d1;
 
+   // Make delayed copies in its own clock domain
+   always @(posedge ser_rx_clk)
+     begin
+       xon_d1 <= xon_rcvd;
+       xon_d2 <= xon_d1;
+       xoff_d1 <= xoff_rcvd;
+       xoff_d2 <= xoff_d1;
+     end
+
+   // Transfer copies to our clock domain, flop once for metastability purposes
    always @(posedge clk)
+     begin
+       xon_ret <= xon_rcvd | xon_d1 | xon_d2;
+       xoff_ret <= xoff_rcvd | xoff_d1 | xoff_d2;
+       xon_ret_d1 <= xon_ret;
+       xoff_ret_d1 <= xoff_ret;
+     end
+   
+   reg [15:0] state;
+   always @(posedge clk)
      if(rst)
        state <= 0;
-     else if(xon_rcvd)
+     else if(xoff_ret_d1)
        state <= 255;
-     else if(xoff_rcvd)
+     else if(xon_ret_d1)
        state <= 0;
      else if(state !=0)
        state <= state - 1;
 
-   assign     inhibit_tx = (state != 0);
+   always @(posedge clk)
+     inhibit_tx <= (state != 0);
    
 endmodule // serdes_fc_tx