[Commit-gnuradio] r8134 - usrp2/trunk/fpga/boot_cpld

[matt]

Author: matt
Date: 2008-03-28 16:21:20 -0600 (Fri, 28 Mar 2008)
New Revision: 8134

Modified:
   usrp2/trunk/fpga/boot_cpld/boot_cpld.ucf
   usrp2/trunk/fpga/boot_cpld/boot_cpld.v
Log:
updated for u2_rev2


Modified: usrp2/trunk/fpga/boot_cpld/boot_cpld.ucf
===================================================================
--- usrp2/trunk/fpga/boot_cpld/boot_cpld.ucf    2008-03-28 22:20:36 UTC (rev 
8133)
+++ usrp2/trunk/fpga/boot_cpld/boot_cpld.ucf    2008-03-28 22:21:20 UTC (rev 
8134)
@@ -1,41 +1,34 @@
-#PACE: Start of Constraints generated by PACE
-
-#PACE: Start of PACE I/O Pin Assignments
-NET "CFG_CCLK"  LOC = "P41"  ; 
-NET "CFG_Din"  LOC = "P37"  ; 
-NET "CFG_DONE"  LOC = "P40"  ; 
-NET "CFG_INIT_B"  LOC = "P38"  ; 
-NET "CFG_PROG_B"  LOC = "P39"  ; 
 NET "CLK_25MHZ"  LOC = "P5"  ; 
 NET "CLK_25MHZ_EN"  LOC = "P6"  ; 
-NET "CPLD_CLK"  LOC = "P13"  ; 
-NET "DEBUG<0>"  LOC = "P43"  ; 
-NET "DEBUG<10>"  LOC = "P34"  ; 
-NET "DEBUG<1>"  LOC = "P44"  ; 
-NET "DEBUG<2>"  LOC = "P1"  ; 
-NET "DEBUG<3>"  LOC = "P2"  ; 
-NET "DEBUG<4>"  LOC = "P3"  ; 
-NET "DEBUG<5>"  LOC = "P29"  ; 
-NET "DEBUG<6>"  LOC = "P30"  ; 
-NET "DEBUG<7>"  LOC = "P31"  ; 
-NET "DEBUG<8>"  LOC = "P32"  ; 
-NET "DEBUG<9>"  LOC = "P33"  ; 
-NET "DONE"  LOC = "P16"  ;
 NET "LED<0>"  LOC = "P12"  ; 
 NET "LED<1>"  LOC = "P8"  ; 
 NET "LED<2>"  LOC = "P7"  ; 
-NET "MODE"  LOC = "P18"  ;
+NET "DEBUG<0>"  LOC = "P1"  ; 
+NET "DEBUG<1>"  LOC = "P2"  ; 
+NET "DEBUG<2>"  LOC = "P3"  ; 
+NET "DEBUG<3>"  LOC = "P29"  ; 
+NET "DEBUG<4>"  LOC = "P30"  ; 
+NET "DEBUG<5>"  LOC = "P31"  ; 
+NET "DEBUG<6>"  LOC = "P32"  ; 
+NET "DEBUG<7>"  LOC = "P33"  ; 
+NET "DEBUG<8>"  LOC = "P34"  ; 
 NET "POR"  LOC = "P42"  ; 
+NET "SD_nCS"  LOC = "P20"  ; 
+NET "SD_Din"  LOC = "P21"  ; 
 NET "SD_CLK"  LOC = "P22"  ; 
+NET "SD_Dout"  LOC = "P23"  ; 
 NET "SD_DAT1"  LOC = "P27"  ; 
 NET "SD_DAT2"  LOC = "P28"  ; 
-NET "SD_Din"  LOC = "P21"  ; 
-NET "SD_Dout"  LOC = "P23"  ; 
-NET "SD_nCS"  LOC = "P20"  ; 
+NET "SD_prot"  LOC = "P19"  ;
+NET "SD_det"  LOC = "P36"  ;
+NET "CFG_INIT_B"  LOC = "P38"  ; 
+NET "CFG_Din"  LOC = "P37"  ; 
+NET "CFG_CCLK"  LOC = "P41"  ; 
+NET "CFG_DONE"  LOC = "P40"  ; 
+NET "CFG_PROG_B"  LOC = "P39"  ; 
+NET "CPLD_CLK"  LOC = "P13"  ; 
 NET "START"  LOC = "P14"  ;
-
-#PACE: Start of PACE Area Constraints
-
-#PACE: Start of PACE Prohibit Constraints
-
-#PACE: End of Constraints generated by PACE
+NET "MODE"  LOC = "P18"  ;
+NET "DONE"  LOC = "P16"  ;
+NET "detached"  LOC = "P43"  ;
+NET "CPLD_misc"  LOC = "P44"  ;

Modified: usrp2/trunk/fpga/boot_cpld/boot_cpld.v
===================================================================
--- usrp2/trunk/fpga/boot_cpld/boot_cpld.v      2008-03-28 22:20:36 UTC (rev 
8133)
+++ usrp2/trunk/fpga/boot_cpld/boot_cpld.v      2008-03-28 22:21:20 UTC (rev 
8134)
@@ -1,55 +1,40 @@
 `timescale 1ns / 1ps
-//////////////////////////////////////////////////////////////////////////////////
-// Company: 
-// Engineer: 
-// 
-// Create Date:    13:26:59 03/31/2007 
-// Design Name: 
-// Module Name:    boot_cpld 
-// Project Name: 
-// Target Devices: 
-// Tool versions: 
-// Description: 
-//
-// Dependencies: 
-//
-// Revision: 
-// Revision 0.01 - File Created
-// Additional Comments: 
-//
-//////////////////////////////////////////////////////////////////////////////////
+// 
////////////////////////////////////////////////////////////////////////////////
+// Boot CPLD design, only for u2_rev2
+// 
////////////////////////////////////////////////////////////////////////////////
+
 module boot_cpld
-  (CLK_25MHZ, CLK_25MHZ_EN, LED, CPLD_CLK, START, MODE, DONE, 
-   SD_nCS, SD_Din, SD_CLK, SD_Dout, SD_DAT1, SD_DAT2, CFG_INIT_B, CFG_Din, 
DEBUG, POR, 
-   CFG_CCLK, CFG_DONE, CFG_PROG_B, detached);
+  (input CLK_25MHZ,
+   output CLK_25MHZ_EN,
+   output [2:0] LED,
+   output [8:0] DEBUG,
+   input        POR,
    
-   input CLK_25MHZ;
-   output CLK_25MHZ_EN;
-   output [2:0] LED;
-   output [10:0] DEBUG;
-   input        POR;
-   
    // To SD Card
-   output       SD_nCS;
-   output       SD_Din;
-   output       SD_CLK;
-   input        SD_Dout;
-   input        SD_DAT1;  // Unused
-   input        SD_DAT2;  // Unused
+   output       SD_nCS,
+   output       SD_Din,
+   output       SD_CLK,
+   input        SD_Dout,
+   input        SD_DAT1,  // Unused
+   input        SD_DAT2,  // Unused
+   input         SD_prot,  // Write Protect
+   input         SD_det,   // Card Detect
    
    // To FPGA Config Interface
-   input        CFG_INIT_B;
-   output       CFG_Din;     // Also used in Data interface
-   output       CFG_CCLK;
-   input        CFG_DONE;
-   output       CFG_PROG_B;
+   input        CFG_INIT_B,
+   output       CFG_Din,     // Also used in Data interface
+   output       CFG_CCLK,
+   input        CFG_DONE,
+   output       CFG_PROG_B,
    
    // To FPGA data interface
-   output       CPLD_CLK;
-   input        START;
-   input        MODE;
-   input        DONE;
-   output       detached; // to RAM_A14 (pin A11 on RAM)
+   output       CPLD_CLK,
+   input        START,
+   input        MODE,
+   input        DONE,
+   output       detached,
+   input         CPLD_misc,   // Unused for now
+   );
    
    assign       CLK_25MHZ_EN = 1'b1;