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[Commit-gnuradio] r8338 - in usrp2/trunk/firmware: apps lib
|
From: |
eb |
|
Subject: |
[Commit-gnuradio] r8338 - in usrp2/trunk/firmware: apps lib |
|
Date: |
Thu, 8 May 2008 20:21:40 -0600 (MDT) |
Author: eb
Date: 2008-05-08 20:21:39 -0600 (Thu, 08 May 2008)
New Revision: 8338
Added:
usrp2/trunk/firmware/lib/db_basic.c
usrp2/trunk/firmware/lib/db_init.c
Modified:
usrp2/trunk/firmware/apps/eth_to_serdes.c
usrp2/trunk/firmware/apps/gen_eth_packets.c
usrp2/trunk/firmware/apps/gen_pause_frames.c
usrp2/trunk/firmware/apps/rcv_eth_packets.c
usrp2/trunk/firmware/apps/rx_only.c
usrp2/trunk/firmware/apps/sd_bounce.c
usrp2/trunk/firmware/apps/sd_gentest.c
usrp2/trunk/firmware/apps/serdes_to_dsp.c
usrp2/trunk/firmware/apps/test_phy_comm.c
usrp2/trunk/firmware/apps/test_serdes.c
usrp2/trunk/firmware/apps/tx_only.c
usrp2/trunk/firmware/apps/tx_standalone.c
usrp2/trunk/firmware/lib/Makefile.am
usrp2/trunk/firmware/lib/db_base.h
usrp2/trunk/firmware/lib/hal_io.c
usrp2/trunk/firmware/lib/hal_io.h
usrp2/trunk/firmware/lib/memory_map.h
usrp2/trunk/firmware/lib/u2_init.c
Log:
work-in-progress on USRP2 daughterboard code, refactored GPIO
handling, ATR, etc.
Modified: usrp2/trunk/firmware/apps/eth_to_serdes.c
===================================================================
--- usrp2/trunk/firmware/apps/eth_to_serdes.c 2008-05-09 02:17:11 UTC (rev
8337)
+++ usrp2/trunk/firmware/apps/eth_to_serdes.c 2008-05-09 02:21:39 UTC (rev
8338)
@@ -125,8 +125,8 @@
// setup tx gpio bits for GPIOM_FPGA_1 -- fpga debug output
- hal_gpio_set_tx_mode(15, 0, GPIOM_FPGA_0);
- hal_gpio_set_rx_mode(15, 0, GPIOM_FPGA_0);
+ //hal_gpio_set_sels(GPIO_TX_BANK, "1111111111111111");
+ //hal_gpio_set_sels(GPIO_RX_BANK, "1111111111111111");
putstr("\neth_to_serdes\n");
Modified: usrp2/trunk/firmware/apps/gen_eth_packets.c
===================================================================
--- usrp2/trunk/firmware/apps/gen_eth_packets.c 2008-05-09 02:17:11 UTC (rev
8337)
+++ usrp2/trunk/firmware/apps/gen_eth_packets.c 2008-05-09 02:21:39 UTC (rev
8338)
@@ -122,8 +122,8 @@
u2_init();
// setup tx gpio bits for GPIOM_FPGA_1 -- fpga debug output
- hal_gpio_set_tx_mode(15, 0, GPIOM_FPGA_1);
- hal_gpio_set_rx_mode(15, 0, GPIOM_FPGA_1);
+ //hal_gpio_set_sels(GPIO_TX_BANK, "1111111111111111");
+ //hal_gpio_set_sels(GPIO_RX_BANK, "1111111111111111");
putstr("\ngen_eth_packets\n");
Modified: usrp2/trunk/firmware/apps/gen_pause_frames.c
===================================================================
--- usrp2/trunk/firmware/apps/gen_pause_frames.c 2008-05-09 02:17:11 UTC
(rev 8337)
+++ usrp2/trunk/firmware/apps/gen_pause_frames.c 2008-05-09 02:21:39 UTC
(rev 8338)
@@ -152,8 +152,8 @@
u2_init();
// setup tx gpio bits for GPIOM_FPGA_1 -- fpga debug output
- hal_gpio_set_tx_mode(15, 0, GPIOM_FPGA_0);
- hal_gpio_set_rx_mode(15, 0, GPIOM_FPGA_0); // no printing...
+ //hal_gpio_set_sels(GPIO_TX_BANK, "1111111111111111");
+ //hal_gpio_set_sels(GPIO_RX_BANK, "1111111111111111");
putstr("\ngen_eth_packets\n");
Modified: usrp2/trunk/firmware/apps/rcv_eth_packets.c
===================================================================
--- usrp2/trunk/firmware/apps/rcv_eth_packets.c 2008-05-09 02:17:11 UTC (rev
8337)
+++ usrp2/trunk/firmware/apps/rcv_eth_packets.c 2008-05-09 02:21:39 UTC (rev
8338)
@@ -92,7 +92,7 @@
break;
}
- hal_gpio_set_tx(v, LS_MASK); /* set debug bits on d'board */
+ //hal_gpio_set_tx(v, LS_MASK); /* set debug bits on d'board */
putstr("\neth link changed: speed = ");
puthex16_nl(speed);
@@ -155,7 +155,8 @@
int peak_hold_count = 0;
// setup tx gpio bits for GPIOM_FPGA_1 -- fpga debug output
- hal_gpio_set_tx_mode(15, 0, GPIOM_FPGA_1);
+ //hal_gpio_set_sels(GPIO_TX_BANK, "1111111111111111");
+ //hal_gpio_set_sels(GPIO_RX_BANK, "1111111111111111");
putstr("\nrcv_eth_packets\n");
Modified: usrp2/trunk/firmware/apps/rx_only.c
===================================================================
--- usrp2/trunk/firmware/apps/rx_only.c 2008-05-09 02:17:11 UTC (rev 8337)
+++ usrp2/trunk/firmware/apps/rx_only.c 2008-05-09 02:21:39 UTC (rev 8338)
@@ -249,8 +249,9 @@
{
u2_init();
- hal_gpio_set_tx_mode(15, 0, GPIOM_FPGA_1);
- hal_gpio_set_rx_mode(15, 0, GPIOM_FPGA_1);
+ // setup tx gpio bits for GPIOM_FPGA_1 -- fpga debug output
+ //hal_gpio_set_sels(GPIO_TX_BANK, "1111111111111111");
+ //hal_gpio_set_sels(GPIO_RX_BANK, "1111111111111111");
putstr("\nrx_only\n");
Modified: usrp2/trunk/firmware/apps/sd_bounce.c
===================================================================
--- usrp2/trunk/firmware/apps/sd_bounce.c 2008-05-09 02:17:11 UTC (rev
8337)
+++ usrp2/trunk/firmware/apps/sd_bounce.c 2008-05-09 02:21:39 UTC (rev
8338)
@@ -132,8 +132,8 @@
//output_regs->clk_ctrl = 0x14;
// setup tx gpio bits for GPIOM_FPGA_1 -- fpga debug output
- hal_gpio_set_tx_mode(15, 0, GPIOM_FPGA_0);
- hal_gpio_set_rx_mode(15, 0, GPIOM_FPGA_0);
+ //hal_gpio_set_sels(GPIO_TX_BANK, "1111111111111111");
+ //hal_gpio_set_sels(GPIO_RX_BANK, "1111111111111111");
putstr("\nsd_bounce\n");
Modified: usrp2/trunk/firmware/apps/sd_gentest.c
===================================================================
--- usrp2/trunk/firmware/apps/sd_gentest.c 2008-05-09 02:17:11 UTC (rev
8337)
+++ usrp2/trunk/firmware/apps/sd_gentest.c 2008-05-09 02:21:39 UTC (rev
8338)
@@ -111,10 +111,9 @@
ad9510_write_reg(0x5A, 0x01); // Update Regs
-
// setup tx gpio bits for GPIOM_FPGA_1 -- fpga debug output
- hal_gpio_set_tx_mode(15, 0, GPIOM_FPGA_0);
- hal_gpio_set_rx_mode(15, 0, GPIOM_FPGA_0);
+ //hal_gpio_set_sels(GPIO_TX_BANK, "1111111111111111");
+ //hal_gpio_set_sels(GPIO_RX_BANK, "1111111111111111");
putstr("\nsd_gentest\n");
Modified: usrp2/trunk/firmware/apps/serdes_to_dsp.c
===================================================================
--- usrp2/trunk/firmware/apps/serdes_to_dsp.c 2008-05-09 02:17:11 UTC (rev
8337)
+++ usrp2/trunk/firmware/apps/serdes_to_dsp.c 2008-05-09 02:21:39 UTC (rev
8338)
@@ -152,8 +152,8 @@
//output_regs->clk_ctrl = 0x14;
// setup tx gpio bits for GPIOM_FPGA_1 -- fpga debug output
- hal_gpio_set_tx_mode(15, 0, GPIOM_FPGA_1);
- hal_gpio_set_rx_mode(15, 0, GPIOM_FPGA_1); // no printing...
+ //hal_gpio_set_sels(GPIO_TX_BANK, "1111111111111111");
+ //hal_gpio_set_sels(GPIO_RX_BANK, "1111111111111111");
putstr("\nserdes_to_dsp\n");
Modified: usrp2/trunk/firmware/apps/test_phy_comm.c
===================================================================
--- usrp2/trunk/firmware/apps/test_phy_comm.c 2008-05-09 02:17:11 UTC (rev
8337)
+++ usrp2/trunk/firmware/apps/test_phy_comm.c 2008-05-09 02:21:39 UTC (rev
8338)
@@ -70,7 +70,7 @@
break;
}
- hal_gpio_set_tx(v, LS_MASK); /* set debug bits on d'board */
+ //hal_gpio_set_tx(v, LS_MASK); /* set debug bits on d'board */
putstr("\neth link changed: speed = ");
puthex_nl(speed);
@@ -95,7 +95,9 @@
pic_register_handler(IRQ_TIMER, timer_handler);
hal_set_timeout(DELTA_T); // schedule timeout
- hal_gpio_set_tx_mode(15, 13, GPIOM_OUTPUT);
+ // setup tx gpio bits for GPIOM_FPGA_1 -- fpga debug output
+ //hal_gpio_set_sels(GPIO_TX_BANK, "1111111111111111");
+ //hal_gpio_set_sels(GPIO_RX_BANK, "1111111111111111");
ethernet_register_link_changed_callback(link_changed_callback);
Modified: usrp2/trunk/firmware/apps/test_serdes.c
===================================================================
--- usrp2/trunk/firmware/apps/test_serdes.c 2008-05-09 02:17:11 UTC (rev
8337)
+++ usrp2/trunk/firmware/apps/test_serdes.c 2008-05-09 02:21:39 UTC (rev
8338)
@@ -88,7 +88,7 @@
break;
}
- hal_gpio_set_tx(v, LS_MASK); /* set debug bits on d'board */
+ //hal_gpio_set_tx(v, LS_MASK); /* set debug bits on d'board */
putstr("\neth link changed: speed = ");
puthex16_nl(speed);
@@ -147,8 +147,8 @@
u2_init();
// setup tx gpio bits for GPIOM_FPGA_1 -- fpga debug output
- hal_gpio_set_tx_mode(15, 0, GPIOM_FPGA_1);
- hal_gpio_set_rx_mode(15, 0, GPIOM_FPGA_1); // no printing...
+ //hal_gpio_set_sels(GPIO_TX_BANK, "1111111111111111");
+ //hal_gpio_set_sels(GPIO_RX_BANK, "1111111111111111");
putstr("\ngen_eth_packets\n");
Modified: usrp2/trunk/firmware/apps/tx_only.c
===================================================================
--- usrp2/trunk/firmware/apps/tx_only.c 2008-05-09 02:17:11 UTC (rev 8337)
+++ usrp2/trunk/firmware/apps/tx_only.c 2008-05-09 02:21:39 UTC (rev 8338)
@@ -138,9 +138,10 @@
u2_init();
// setup tx gpio bits for GPIOM_FPGA_1 -- fpga debug output
- hal_gpio_set_tx_mode(15, 0, GPIOM_FPGA_1);
- hal_gpio_set_rx_mode(15, 0, GPIOM_FPGA_1); // no printing...
+ //hal_gpio_set_sels(GPIO_TX_BANK, "1111111111111111");
+ //hal_gpio_set_sels(GPIO_RX_BANK, "1111111111111111");
+
putstr("\ntx_only\n");
ethernet_register_link_changed_callback(link_changed_callback);
Modified: usrp2/trunk/firmware/apps/tx_standalone.c
===================================================================
--- usrp2/trunk/firmware/apps/tx_standalone.c 2008-05-09 02:17:11 UTC (rev
8337)
+++ usrp2/trunk/firmware/apps/tx_standalone.c 2008-05-09 02:21:39 UTC (rev
8338)
@@ -248,8 +248,8 @@
u2_init();
// setup tx gpio bits for GPIOM_FPGA_1 -- fpga debug output
- hal_gpio_set_tx_mode(15, 0, GPIOM_FPGA_1);
- hal_gpio_set_rx_mode(15, 0, GPIOM_FPGA_1); // no printing...
+ //hal_gpio_set_sels(GPIO_TX_BANK, "1111111111111111");
+ //hal_gpio_set_sels(GPIO_RX_BANK, "1111111111111111");
putstr("\ntx_only\n");
@@ -330,7 +330,7 @@
break;
}
- hal_gpio_set_tx(v, LS_MASK); /* set debug bits on d'board */
+ //hal_gpio_set_tx(v, LS_MASK); /* set debug bits on d'board */
// hal_set_leds(link_is_up ? 0x2 : 0x0, 0x2);
Modified: usrp2/trunk/firmware/lib/Makefile.am
===================================================================
--- usrp2/trunk/firmware/lib/Makefile.am 2008-05-09 02:17:11 UTC (rev
8337)
+++ usrp2/trunk/firmware/lib/Makefile.am 2008-05-09 02:21:39 UTC (rev
8338)
@@ -24,6 +24,8 @@
ad9510.c \
ad9777.c \
buffer_pool.c \
+ db_basic.c \
+ db_init.c \
db_rfx.c \
dbsm.c \
eeprom.c \
Modified: usrp2/trunk/firmware/lib/db_base.h
===================================================================
--- usrp2/trunk/firmware/lib/db_base.h 2008-05-09 02:17:11 UTC (rev 8337)
+++ usrp2/trunk/firmware/lib/db_base.h 2008-05-09 02:21:39 UTC (rev 8338)
@@ -51,10 +51,10 @@
uint32_t atr_rxval; //< value to use when receiving
//! delay in clk ticks from when Tx fifo gets data to when T/R switches
- uint32_t atr_tx_delay;
+ // uint32_t atr_tx_delay;
//! delay in clk ticks from when Tx fifo goes empty to when T/R switches
- uint32_t atr_rx_delay;
+ // uint32_t atr_rx_delay;
bool (*init)(struct db_base *);
bool (*set_freq)(struct db_base *, u2_fxpt_freq_t freq, u2_fxpt_freq_t *dc);
Added: usrp2/trunk/firmware/lib/db_basic.c
===================================================================
--- usrp2/trunk/firmware/lib/db_basic.c (rev 0)
+++ usrp2/trunk/firmware/lib/db_basic.c 2008-05-09 02:21:39 UTC (rev 8338)
@@ -0,0 +1,157 @@
+/* -*- c++ -*- */
+/*
+ * Copyright 2008 Free Software Foundation, Inc.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+
+#include <db_base.h>
+
+bool db_basic_init(struct db_base *db);
+bool db_basic_set_freq(struct db_base *db, u2_fxpt_freq_t freq, u2_fxpt_freq_t
*dc);
+bool db_basic_set_gain(struct db_base *db, u2_fxpt_gain_t gain);
+bool db_basic_set_tx_enable(struct db_base *, bool on);
+
+struct db_basic {
+ struct db_base base;
+};
+
+
+struct db_basic db_basic_tx = {
+ .base.dbid = 0x0000,
+ .base.output_enables = 0x0000,
+ .base.used_pins = 0x0000,
+ .base.freq_min = U2_DOUBLE_TO_FXPT_FREQ(-90e9),
+ .base.freq_max = U2_DOUBLE_TO_FXPT_FREQ(90e9),
+ .base.freq_step_size = U2_DOUBLE_TO_FXPT_FREQ(1e-6),
+ .base.gain_min = U2_DOUBLE_TO_FXPT_GAIN(0),
+ .base.gain_max = U2_DOUBLE_TO_FXPT_GAIN(0),
+ .base.gain_step_size = U2_DOUBLE_TO_FXPT_GAIN(0),
+ .base.is_quadrature = true,
+ .base.i_and_q_swapped = false,
+ .base.spectrum_inverted = false,
+ .base.lo_offset = U2_DOUBLE_TO_FXPT_FREQ(0),
+ .base.atr_mask = 0,
+ .base.atr_txval = 0,
+ .base.atr_rxval = 0,
+ //.base.atr_tx_delay = 0,
+ //.base.atr_rx_delay = 0,
+
+ .base.set_freq = db_basic_set_freq,
+ .base.set_gain = db_basic_set_gain,
+ .base.set_tx_enable = db_basic_set_tx_enable,
+};
+
+struct db_basic db_basic_rx = {
+ .base.dbid = 0x0001,
+ .base.output_enables = 0x0000,
+ .base.used_pins = 0x0000,
+ .base.freq_min = U2_DOUBLE_TO_FXPT_FREQ(-90e9),
+ .base.freq_max = U2_DOUBLE_TO_FXPT_FREQ(90e9),
+ .base.freq_step_size = U2_DOUBLE_TO_FXPT_FREQ(1e-6),
+ .base.gain_min = U2_DOUBLE_TO_FXPT_GAIN(0),
+ .base.gain_max = U2_DOUBLE_TO_FXPT_GAIN(0),
+ .base.gain_step_size = U2_DOUBLE_TO_FXPT_GAIN(0),
+ .base.is_quadrature = false,
+ .base.i_and_q_swapped = false,
+ .base.spectrum_inverted = false,
+ .base.lo_offset = U2_DOUBLE_TO_FXPT_FREQ(0),
+ .base.atr_mask = 0,
+ .base.atr_txval = 0,
+ .base.atr_rxval = 0,
+ //.base.atr_tx_delay = 0,
+ //.base.atr_rx_delay = 0,
+
+ .base.set_freq = db_basic_set_freq,
+ .base.set_gain = db_basic_set_gain,
+ .base.set_tx_enable = db_basic_set_tx_enable,
+};
+
+struct db_basic db_lf_tx = {
+ .base.dbid = 0x000e,
+ .base.output_enables = 0x0000,
+ .base.used_pins = 0x0000,
+ .base.freq_min = U2_DOUBLE_TO_FXPT_FREQ(-32e6),
+ .base.freq_max = U2_DOUBLE_TO_FXPT_FREQ(32e6),
+ .base.freq_step_size = U2_DOUBLE_TO_FXPT_FREQ(1e-6),
+ .base.gain_min = U2_DOUBLE_TO_FXPT_GAIN(0),
+ .base.gain_max = U2_DOUBLE_TO_FXPT_GAIN(0),
+ .base.gain_step_size = U2_DOUBLE_TO_FXPT_GAIN(0),
+ .base.is_quadrature = true,
+ .base.i_and_q_swapped = false,
+ .base.spectrum_inverted = false,
+ .base.lo_offset = U2_DOUBLE_TO_FXPT_FREQ(0),
+ .base.atr_mask = 0,
+ .base.atr_txval = 0,
+ .base.atr_rxval = 0,
+ //.base.atr_tx_delay = 0,
+ //.base.atr_rx_delay = 0,
+
+ .base.set_freq = db_basic_set_freq,
+ .base.set_gain = db_basic_set_gain,
+ .base.set_tx_enable = db_basic_set_tx_enable,
+};
+
+struct db_basic db_lf_rx = {
+ .base.dbid = 0x000f,
+ .base.output_enables = 0x0000,
+ .base.used_pins = 0x0000,
+ .base.freq_min = U2_DOUBLE_TO_FXPT_FREQ(0),
+ .base.freq_max = U2_DOUBLE_TO_FXPT_FREQ(32e6),
+ .base.freq_step_size = U2_DOUBLE_TO_FXPT_FREQ(1e-6),
+ .base.gain_min = U2_DOUBLE_TO_FXPT_GAIN(0),
+ .base.gain_max = U2_DOUBLE_TO_FXPT_GAIN(0),
+ .base.gain_step_size = U2_DOUBLE_TO_FXPT_GAIN(0),
+ .base.is_quadrature = false,
+ .base.i_and_q_swapped = false,
+ .base.spectrum_inverted = false,
+ .base.lo_offset = U2_DOUBLE_TO_FXPT_FREQ(0),
+ .base.atr_mask = 0,
+ .base.atr_txval = 0,
+ .base.atr_rxval = 0,
+ //.base.atr_tx_delay = 0,
+ //.base.atr_rx_delay = 0,
+
+ .base.set_freq = db_basic_set_freq,
+ .base.set_gain = db_basic_set_gain,
+ .base.set_tx_enable = db_basic_set_tx_enable,
+};
+
+
+bool
+db_basic_init(struct db_base *db)
+{
+ return true;
+}
+
+bool
+db_basic_set_freq(struct db_base *db, u2_fxpt_freq_t freq, u2_fxpt_freq_t *dc)
+{
+ *dc = 0;
+ return true;
+}
+
+bool
+db_basic_set_gain(struct db_base *db, u2_fxpt_gain_t gain)
+{
+ return true;
+}
+
+bool
+db_basic_set_tx_enable(struct db_base *db, bool on)
+{
+ return true;
+}
+
Property changes on: usrp2/trunk/firmware/lib/db_basic.c
___________________________________________________________________
Name: svn:eol-style
+ native
Added: usrp2/trunk/firmware/lib/db_init.c
===================================================================
--- usrp2/trunk/firmware/lib/db_init.c (rev 0)
+++ usrp2/trunk/firmware/lib/db_init.c 2008-05-09 02:21:39 UTC (rev 8338)
@@ -0,0 +1,157 @@
+/* -*- c++ -*- */
+/*
+ * Copyright 2008 Free Software Foundation, Inc.
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+
+#include <memory_map.h>
+#include <i2c.h>
+#include <usrp2_i2c_addr.h>
+#include <string.h>
+#include <stdio.h>
+#include <db_base.h>
+#include <hal_io.h>
+
+
+struct db_base *tx_dboard; // the tx daughterboard that's installed
+struct db_base *rx_dboard; // the rx daughterboard that's installed
+
+extern struct db_base db_basic_tx;
+extern struct db_base db_basic_rx;
+extern struct db_base db_lf_tx;
+extern struct db_base db_lf_rx;
+extern struct db_base db_rfx_400_tx;
+extern struct db_base db_rfx_400_rx;
+
+struct db_base *all_dboards[] = {
+ &db_basic_tx,
+ &db_basic_rx,
+ &db_lf_tx,
+ &db_lf_rx,
+ &db_rfx_400_tx,
+ &db_rfx_400_rx,
+ 0
+};
+
+
+typedef enum { UDBE_OK, UDBE_NO_EEPROM, UDBE_INVALID_EEPROM }
usrp_dbeeprom_status_t;
+
+static usrp_dbeeprom_status_t
+read_raw_dboard_eeprom (unsigned char *buf, int i2c_addr)
+{
+ if (!eeprom_read (i2c_addr, 0, buf, DB_EEPROM_CLEN))
+ return UDBE_NO_EEPROM;
+
+ if (buf[DB_EEPROM_MAGIC] != DB_EEPROM_MAGIC_VALUE)
+ return UDBE_INVALID_EEPROM;
+
+ int sum = 0;
+ unsigned int i;
+ for (i = 0; i < DB_EEPROM_CLEN; i++)
+ sum += buf[i];
+
+ if ((sum & 0xff) != 0)
+ return UDBE_INVALID_EEPROM;
+
+ return UDBE_OK;
+}
+
+
+/*
+ * Return DBID, -1 <none> or -2 <invalid eeprom contents>
+ */
+static int
+read_dboard_eeprom(int i2c_addr)
+{
+ unsigned char buf[DB_EEPROM_CLEN];
+
+ usrp_dbeeprom_status_t s = read_raw_dboard_eeprom (buf, i2c_addr);
+ switch (s){
+ default:
+ case UDBE_NO_EEPROM:
+ return -1;
+ case UDBE_INVALID_EEPROM:
+ return -2;
+ case UDBE_OK:
+ return (buf[DB_EEPROM_ID_MSB] << 8) | buf[DB_EEPROM_ID_LSB];
+ }
+}
+
+
+static struct db_base *
+lookup_dbid(int dbid)
+{
+ if (dbid < 0)
+ return 0;
+
+ int i;
+ for (i = 0; all_dboards[i]; i++)
+ if (all_dboards[i]->dbid == dbid)
+ return all_dboards[i];
+
+ return 0;
+}
+
+static struct db_base *
+lookup_dboard(int i2c_addr, struct db_base *default_db, char *msg)
+{
+ struct db_base *db;
+ int dbid = read_dboard_eeprom(i2c_addr);
+ printf("%s dbid: 0x%x\n", msg, dbid);
+
+ if (dbid < 0){ // there was some kind of problem. Treat as Basic Tx
+ return default_db;
+ }
+ else if ((db = lookup_dbid(dbid)) == 0){
+ return default_db;
+ printf("No daugherboard code for dbid = 0x%x\n", dbid);
+ }
+ return db;
+}
+
+static void
+set_gpio_mode(int bank, struct db_base *db)
+{
+ int i;
+
+ hal_gpio_set_ddr(bank, db->output_enables, 0xffff);
+
+ // Copy ATR values into controller
+ atr_regs->v[ATR_IDLE] = db->atr_rxval; // Rx
+ atr_regs->v[ATR_RX] = db->atr_rxval; // Rx
+ atr_regs->v[ATR_TX] = db->atr_txval; // Tx
+ atr_regs->v[ATR_FULL] = db->atr_rxval; // Rx
+
+ for (i = 0; i < 16; i++){
+ if (db->used_pins & (1 << i)){
+ // set to either GPIO_SEL_SW or GPIO_SEL_ATR
+ hal_gpio_set_sel(bank, i, (db->atr_mask & (1 << 1)) ? 'a' : 's');
+ }
+ }
+}
+
+void
+db_init(void)
+{
+
+ tx_dboard = lookup_dboard(I2C_ADDR_TX_A, &db_basic_tx, "Tx");
+ set_gpio_mode(GPIO_TX_BANK, tx_dboard);
+ tx_dboard->init(tx_dboard);
+
+ rx_dboard = lookup_dboard(I2C_ADDR_RX_A, &db_basic_rx, "Rx");
+ set_gpio_mode(GPIO_RX_BANK, rx_dboard);
+ rx_dboard->init(rx_dboard);
+}
Property changes on: usrp2/trunk/firmware/lib/db_init.c
___________________________________________________________________
Name: svn:eol-style
+ native
Modified: usrp2/trunk/firmware/lib/hal_io.c
===================================================================
--- usrp2/trunk/firmware/lib/hal_io.c 2008-05-09 02:17:11 UTC (rev 8337)
+++ usrp2/trunk/firmware/lib/hal_io.c 2008-05-09 02:21:39 UTC (rev 8338)
@@ -21,65 +21,137 @@
#include "hal_io.h"
#include "memory_map.h"
#include "hal_uart.h"
+#include "bool.h"
#include <stdio.h>
+#include <string.h>
+//#include <assert.h>
-unsigned int
-hal_gpio_mode_mask(int high_bitno, int low_bitno, int mode)
+/*
+ * ========================================================================
+ * GPIOS
+ * ========================================================================
+ */
+void
+hal_gpio_set_ddr(int bank, int value, int mask)
{
- mode &= 0x3;
- unsigned int t = 0;
+ bank &= 0x1;
- int i;
- for (i = 15; i >= 0; i--){
- t <<= 2;
- if (i <= high_bitno && i >= low_bitno)
- t |= mode;
+ if (bank == GPIO_TX_BANK){ // tx in top half
+ value <<= 16;
+ mask <<= 16;
}
- return t;
-}
+ else {
+ value &= 0xffff;
+ mask &= 0xffff;
+ }
-void
-hal_gpio_set_rx_mode(int high_bitno, int low_bitno, int mode)
-{
- unsigned mask = hal_gpio_mode_mask(high_bitno, low_bitno, 0x3);
- unsigned val = hal_gpio_mode_mask(high_bitno, low_bitno, mode);
int ei = hal_disable_ints();
- gpio_base->rx_mode = (gpio_base->rx_mode & ~mask) | (val & mask);
+ gpio_base->ddr = (gpio_base->ddr & ~mask) | (value & mask);
hal_restore_ints(ei);
}
+static bool
+code_to_int(char code, int *val)
+{
+ switch(code){
+ case 's': *val = GPIO_SEL_SW; return true;
+ case 'a': *val = GPIO_SEL_ATR; return true;
+ case '0': *val = GPIO_SEL_DEBUG_0; return true;
+ case '1': *val = GPIO_SEL_DEBUG_1; return true;
+ case '.':
+ default:
+ return false;
+ }
+}
+
void
-hal_gpio_set_tx_mode(int high_bitno, int low_bitno, int mode)
+hal_gpio_set_sel(int bank, int bitno, char code)
{
- unsigned mask = hal_gpio_mode_mask(high_bitno, low_bitno, 0x3);
- unsigned val = hal_gpio_mode_mask(high_bitno, low_bitno, mode);
+ bank &= 0x1;
+ int t;
+
+ if (!code_to_int(code, &t))
+ return;
+
+ int val = t << (2 * bitno);
+ int mask = 0x3 << (2 * bitno);
+
+ volatile uint32_t *sel = bank == GPIO_TX_BANK ? &gpio_base->tx_sel :
&gpio_base->rx_sel;
int ei = hal_disable_ints();
- gpio_base->tx_mode = (gpio_base->tx_mode & ~mask) | (val & mask);
+ *sel = (*sel & ~mask) | (val & mask);
hal_restore_ints(ei);
}
-// in top 16-bits of io reg
void
-hal_gpio_set_tx(int value, int mask)
+hal_gpio_set_sels(int bank, char *codes)
{
- value <<= 16;
- mask <<= 16;
+ //assert(strlen(codes) == 16);
+
+ int val = 0;
+ int mask = 0;
+ int i;
+
+ for (i = 15; i >= 0; i--){
+ val <<= 2;
+ mask <<= 2;
+ int t;
+ if (code_to_int(codes[i], &t)){
+ val |= t;
+ mask |= 0x3;
+ }
+ }
+
+ volatile uint32_t *sel = bank == GPIO_TX_BANK ? &gpio_base->tx_sel :
&gpio_base->rx_sel;
int ei = hal_disable_ints();
- gpio_base->io = (gpio_base->io & ~mask) | (value & mask);
+ *sel = (*sel & ~mask) | (val & mask);
hal_restore_ints(ei);
}
-// in bottom 16-bits of io reg
+
+/*!
+ * \brief write \p value to gpio pins specified by \p mask.
+ */
void
-hal_gpio_set_rx(int value, int mask)
+hal_gpio_write(int bank, int value, int mask)
{
- value &= 0xffff;
- mask &= 0xffff;
+ bank &= 0x1;
+
+ if (bank == GPIO_TX_BANK){ // tx in top half
+ value <<= 16;
+ mask <<= 16;
+ }
+ else {
+ value &= 0xffff;
+ mask &= 0xffff;
+ }
+
int ei = hal_disable_ints();
gpio_base->io = (gpio_base->io & ~mask) | (value & mask);
hal_restore_ints(ei);
}
+
+/*!
+ * \brief read GPIO bits
+ */
+int
+hal_gpio_read(int bank)
+{
+ bank &= 0x1;
+ int r = gpio_base->io;
+ if (bank == GPIO_TX_BANK)
+ r >>= 16;
+
+ return r & 0xffff;
+}
+
+
+/*
+ * ========================================================================
+ * leds
+ * ========================================================================
+ */
+
static unsigned long leds_shadow = 0;
void
Modified: usrp2/trunk/firmware/lib/hal_io.h
===================================================================
--- usrp2/trunk/firmware/lib/hal_io.h 2008-05-09 02:17:11 UTC (rev 8337)
+++ usrp2/trunk/firmware/lib/hal_io.h 2008-05-09 02:21:39 UTC (rev 8338)
@@ -25,16 +25,89 @@
void hal_finish();
-void hal_gpio_set_rx_mode(int high_bitno, int low_bitno, int mode);
-void hal_gpio_set_tx_mode(int high_bitno, int low_bitno, int mode);
+/*
+ * ------------------------------------------------------------------------
+ * The GPIO pins are organized into two banks of 16-bits.
+ * Bank 0 goes to the Tx daughterboard, Bank 1 goes to the Rx daughterboard.
+ *
+ * Each pin may be configured as an input or an output from the FPGA.
+ * For output pins, there are four signals which may be routed to the
+ * pin. The four signals are the value written by s/w, the output of
+ * the ATR controller, or two different sources of debug info from the
+ * FPGA fabric.
+ * ------------------------------------------------------------------------
+ */
-void hal_gpio_set_tx(int value, int mask);
-void hal_gpio_set_rx(int value, int mask);
+#define GPIO_TX_BANK 0 // pins that connect to the Tx daughterboard
+#define GPIO_RX_BANK 1 // pins that connect to the Rx
daughterboard
+
+/*!
+ * \brief Set the data direction for GPIO pins
+ *
+ * If the bit is set, it's an output from the FPGA.
+ * \param value is a 16-bit bitmask of values
+ * \param mask is a 16-bit bitmask of which bits to effect.
+ */
+void hal_gpio_set_ddr(int bank, int value, int mask);
+
+/*!
+ * \brief Select the source of the signal for an output pin.
+ *
+ * \param code is is one of 's', 'a', '0', '1'
+ * where 's' selects software output, 'a' selects ATR output, '0' selects
+ * debug 0, '1' selects debug 1.
+ */
+void hal_gpio_set_sel(int bank, int bitno, char code);
+
+/*!
+ * \brief Select the source of the signal for the output pins.
+ *
+ * \param codes is is a string of 16 characters composed of '.', 's',
+ * 'a', '0', or '1' where '.' means "don't change", 's' selects
+ * software output, 'a' selects ATR output, '0' selects debug 0, '1'
+ * selects debug 1.
+ */
+void hal_gpio_set_sels(int bank, char *codes);
+
+
+/*!
+ * \brief write \p value to gpio pins specified by \p mask.
+ */
+void hal_gpio_write(int bank, int value, int mask);
+
+/*!
+ * \brief read GPIO bits
+ */
+int hal_gpio_read(int bank);
+
+
+/*
+ * ------------------------------------------------------------------------
+ * control the leds
+ *
+ * Low 4-bits are the general purpose leds on the board
+ * The next bit is the led on the ethernet connector
+ * ------------------------------------------------------------------------
+ */
+
+#define LED_0 0x0001
+#define LED_1 0x0002
+#define LED_3 0x0004
+#define LED_4 0x0008
+#define LED_ETH_CONN 0x0010
+
void hal_set_leds(int value, int mask);
void hal_toggle_leds(int mask);
+/*
+ * ------------------------------------------------------------------------
+ * simple timeouts
+ * ------------------------------------------------------------------------
+ */
+
+
static inline void
hal_set_timeout(int delta_ticks)
{
@@ -44,6 +117,12 @@
timer_regs->time = t;
}
+/*
+ * ------------------------------------------------------------------------
+ * interrupt enable/disable
+ * ------------------------------------------------------------------------
+ */
+
/*!
* \brief Disable interrupts and return previous interrupt enable state.
* [Microblaze specific]
Modified: usrp2/trunk/firmware/lib/memory_map.h
===================================================================
--- usrp2/trunk/firmware/lib/memory_map.h 2008-05-09 02:17:11 UTC (rev
8337)
+++ usrp2/trunk/firmware/lib/memory_map.h 2008-05-09 02:21:39 UTC (rev
8338)
@@ -151,14 +151,14 @@
volatile uint32_t io; // tx data in high 16, rx in low 16
volatile uint32_t tx_sel; // 16 2-bit fields select which source goes
to TX DB
volatile uint32_t rx_sel; // 16 2-bit fields select which source goes
to RX DB
- volatile uint32_t ddr; // 32 bits, 1 means output
+ volatile uint32_t ddr; // 32 bits, 1 means output. tx in high 16,
rx in low 16
} gpio_regs_t;
-// each 2-bit mode field is layed out this way
-#define GPIOM_SW 0 // if pin is an output, set by software in the io reg
-#define GPIOM_ATR 1 // if pin is an output, set by ATR logic
-#define GPIOM_DEBUG_0 2 // if pin is an output, debug lines from FPGA
fabric
-#define GPIOM_DEBUG_1 3 // if pin is an output, debug lines from FPGA
fabric
+// each 2-bit sel field is layed out this way
+#define GPIO_SEL_SW 0 // if pin is an output, set by software in the io
reg
+#define GPIO_SEL_ATR 1 // if pin is an output, set by ATR logic
+#define GPIO_SEL_DEBUG_0 2 // if pin is an output, debug lines from
FPGA fabric
+#define GPIO_SEL_DEBUG_1 3 // if pin is an output, debug lines from
FPGA fabric
#define gpio_base ((gpio_regs_t *) GPIO_BASE)
@@ -466,7 +466,8 @@
#define IRQ_PHY 4 // ethernet PHY
#define IRQ_UNDERRUN 5
#define IRQ_OVERRUN 6
-#define IRQ_UART 7
+#define IRQ_PPS 7 // pulse per second
+#define IRQ_UART 8
#define IRQ_TO_MASK(x) (1 << (x))
@@ -477,6 +478,7 @@
#define PIC_PHY_INT IRQ_TO_MASK(IRQ_PHY)
#define PIC_UNDERRUN_INT IRQ_TO_MASK(IRQ_UNDERRUN)
#define PIC_OVERRUN_INT IRQ_TO_MASK(IRQ_OVERRUN)
+#define PIC_PPS_INT IRQ_TO_MASK(IRQ_PPS)
#define PIC_UART_INT IRQ_TO_MASK(IRQ_UART)
@@ -513,8 +515,17 @@
#define ATR_BASE 0xE400
-#define atr_regs ((int *) ATR_BASE)
+typedef struct {
+ volatile uint32_t v[16];
+} atr_regs_t;
+#define ATR_IDLE 0x0 // indicies into v
+#define ATR_TX 0x1
+#define ATR_RX 0x2
+#define ATR_FULL 0x3
+
+#define atr_regs ((atr_regs_t *) ATR_BASE)
+
///////////////////////////////////////////////////
// Time Sync Controller, Slave 12
Modified: usrp2/trunk/firmware/lib/u2_init.c
===================================================================
--- usrp2/trunk/firmware/lib/u2_init.c 2008-05-09 02:17:11 UTC (rev 8337)
+++ usrp2/trunk/firmware/lib/u2_init.c 2008-05-09 02:21:39 UTC (rev 8338)
@@ -29,8 +29,11 @@
#include "mdelay.h"
#include "ad9777.h"
#include "ad9510.h"
+
//#include "nonstdio.h"
+void db_init(void);
+
/*
* We ought to arrange for this to be called before main, but for now,
* we require that the user's main call u2_init as the first thing...
@@ -39,12 +42,10 @@
u2_init(void)
{
// Set GPIOs to inputs
- hal_gpio_set_rx_mode(15, 0, GPIOM_INPUT);
- hal_gpio_set_tx_mode(15, 0, GPIOM_INPUT);
+ hal_gpio_set_ddr(GPIO_TX_BANK, 0x0000, 0xffff);
+ hal_gpio_set_ddr(GPIO_RX_BANK, 0x0000, 0xffff);
gpio_base->io = 0x00000000;
- hal_gpio_set_tx_mode(15, 15, GPIOM_FPGA_1); // uart output on tx:15
-
hal_io_init();
// init spi, so that we can switch over to the high-speed clock
@@ -167,7 +168,8 @@
i2c_init();
lsadc_init(); // low-speed ADCs
lsdac_init(); // low-speed DACs
-
+ db_init(); // daughterboard init
+
hal_enable_ints();
// flash both leds to let us know board is alive
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