[Commit-gnuradio] r8360 - usrp2/trunk/firmware/lib

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[Commit-gnuradio] r8360 - usrp2/trunk/firmware/lib

From:	matt
Subject:	[Commit-gnuradio] r8360 - usrp2/trunk/firmware/lib
Date:	Sat, 10 May 2008 12:57:40 -0600 (MDT)
Author: matt
Date: 2008-05-10 12:57:40 -0600 (Sat, 10 May 2008)
New Revision: 8360

Modified:
   usrp2/trunk/firmware/lib/db_rfx.c
Log:
handles 900, 1200, 1800, and 2400.  Untested


Modified: usrp2/trunk/firmware/lib/db_rfx.c
===================================================================
--- usrp2/trunk/firmware/lib/db_rfx.c   2008-05-10 18:00:26 UTC (rev 8359)
+++ usrp2/trunk/firmware/lib/db_rfx.c   2008-05-10 18:57:40 UTC (rev 8360)
@@ -62,8 +62,9 @@
 #define ANT_SW  (1 << 6)   // On TX DB, 0 = TX, 1 = RX, on RX DB 0 = main ant, 
1 = RX2
 #define MIX_EN  (1 << 5)   // Enable appropriate mixer
 #define LOCKDET_MASK (1 << 2)   // Input pin
+
 struct db_rfx_common {
-  // RFX common stuff here (if any)
+  // RFX common stuff
   unsigned char DIV2;
   unsigned char CP1;
   unsigned char CP2;
@@ -80,21 +81,54 @@
 struct db_rfx_400_rx {
   struct db_base       base;
   struct db_rfx_common common;
+};
 
-  // RFX 400 rx stuff goes here
-  
+struct db_rfx_400_tx {
+  struct db_base       base;
+  struct db_rfx_common common;
 };
 
+struct db_rfx_900_rx {
+  struct db_base       base;
+  struct db_rfx_common common;
+};
 
-struct db_rfx_400_tx {
+struct db_rfx_900_tx {
   struct db_base       base;
   struct db_rfx_common common;
+};
 
-  // RFX 400 tx stuff goes here
-  
+struct db_rfx_1200_rx {
+  struct db_base       base;
+  struct db_rfx_common common;
 };
 
+struct db_rfx_1200_tx {
+  struct db_base       base;
+  struct db_rfx_common common;
+};
 
+struct db_rfx_1800_rx {
+  struct db_base       base;
+  struct db_rfx_common common;
+};
+
+struct db_rfx_1800_tx {
+  struct db_base       base;
+  struct db_rfx_common common;
+};
+
+struct db_rfx_2400_rx {
+  struct db_base       base;
+  struct db_rfx_common common;
+};
+
+struct db_rfx_2400_tx {
+  struct db_base       base;
+  struct db_rfx_common common;
+};
+
+
 /*
  * The class instances
  */
@@ -161,6 +195,260 @@
   .common.freq_mult = 2
 };
 
+struct db_rfx_900_rx db_rfx_900_rx = {
+  .base.dbid = 0x0025,
+  .base.is_tx = false,
+  .base.output_enables = 0x00E0,
+  .base.used_pins = 0x00FF,
+  //.base.freq_min = U2_DOUBLE_TO_FXPT_FREQ(xxx),
+  //.base.freq_max = U2_DOUBLE_TO_FXPT_FREQ(xxx),
+  //.base.freq_step_size = U2_DOUBLE_TO_FXPT_FREQ(xxx),
+  //.base.gain_min = U2_DOUBLE_TO_FXPT_GAIN(xxx),
+  //.base.gain_max = U2_DOUBLE_TO_FXPT_GAIN(xxx),
+  //.base.gain_step_size = U2_DOUBLE_TO_FXPT_GAIN(xxx),
+  .base.is_quadrature = true,
+  .base.i_and_q_swapped = false,
+  .base.spectrum_inverted = false,
+  //.base.lo_offset = U2_DOUBLE_TO_FXPT_FREQ(4e6),
+  .base.init = rfx_init_rx,
+  .base.set_freq = rfx_set_freq,
+  .base.set_gain = rfx_set_gain,
+  .base.set_tx_enable = 0,
+  .base.atr_mask = 0x00E0,
+  .base.atr_txval = 0,
+  .base.atr_rxval = MIX_EN,
+  // .base.atr_tx_delay =
+  // .base.atr_rx_delay =
+  .common.DIV2 = 1,
+  .common.CP1 = 7,
+  .common.CP2 = 7,
+  .common.spi_mask = SPI_SS_RX_DB,
+  .common.freq_mult = 2
+};
+
+
+struct db_rfx_900_tx db_rfx_900_tx = {
+  .base.dbid = 0x0029,
+  .base.is_tx = true,
+  .base.output_enables = 0x00E0,
+  .base.used_pins = 0x00FF,
+  //.base.freq_min = U2_DOUBLE_TO_FXPT_FREQ(xxx),
+  //.base.freq_max = U2_DOUBLE_TO_FXPT_FREQ(xxx),
+  //.base.freq_step_size = U2_DOUBLE_TO_FXPT_FREQ(xxx),
+  //.base.gain_min = U2_DOUBLE_TO_FXPT_GAIN(xxx),
+  //.base.gain_max = U2_DOUBLE_TO_FXPT_GAIN(xxx),
+  //.base.gain_step_size = U2_DOUBLE_TO_FXPT_GAIN(xxx),
+  .base.is_quadrature = true,
+  .base.i_and_q_swapped = false,
+  .base.spectrum_inverted = false,
+  //.base.lo_offset = U2_DOUBLE_TO_FXPT_FREQ(4e6),
+  .base.init = rfx_init_tx,
+  .base.set_freq = rfx_set_freq,
+  .base.set_gain = rfx_set_gain,
+  .base.set_tx_enable = rfx_set_tx_enable,
+  .base.atr_mask = 0x00E0,
+  .base.atr_txval = MIX_EN, 
+  .base.atr_rxval = ANT_SW,
+  // .base.atr_tx_delay =
+  // .base.atr_rx_delay =
+  .common.DIV2 = 1,
+  .common.CP1 = 7,
+  .common.CP2 = 7,
+  .common.spi_mask = SPI_SS_TX_DB,
+  .common.freq_mult = 2
+};
+
+struct db_rfx_1200_rx db_rfx_1200_rx = {
+  .base.dbid = 0x0026,
+  .base.is_tx = false,
+  .base.output_enables = 0x00E0,
+  .base.used_pins = 0x00FF,
+  //.base.freq_min = U2_DOUBLE_TO_FXPT_FREQ(xxx),
+  //.base.freq_max = U2_DOUBLE_TO_FXPT_FREQ(xxx),
+  //.base.freq_step_size = U2_DOUBLE_TO_FXPT_FREQ(xxx),
+  //.base.gain_min = U2_DOUBLE_TO_FXPT_GAIN(xxx),
+  //.base.gain_max = U2_DOUBLE_TO_FXPT_GAIN(xxx),
+  //.base.gain_step_size = U2_DOUBLE_TO_FXPT_GAIN(xxx),
+  .base.is_quadrature = true,
+  .base.i_and_q_swapped = false,
+  .base.spectrum_inverted = false,
+  //.base.lo_offset = U2_DOUBLE_TO_FXPT_FREQ(4e6),
+  .base.init = rfx_init_rx,
+  .base.set_freq = rfx_set_freq,
+  .base.set_gain = rfx_set_gain,
+  .base.set_tx_enable = 0,
+  .base.atr_mask = 0x00E0,
+  .base.atr_txval = 0,
+  .base.atr_rxval = MIX_EN,
+  // .base.atr_tx_delay =
+  // .base.atr_rx_delay =
+  .common.DIV2 = 1,
+  .common.CP1 = 7,
+  .common.CP2 = 7,
+  .common.spi_mask = SPI_SS_RX_DB,
+  .common.freq_mult = 2
+};
+
+
+struct db_rfx_1200_tx db_rfx_1200_tx = {
+  .base.dbid = 0x002a,
+  .base.is_tx = true,
+  .base.output_enables = 0x00E0,
+  .base.used_pins = 0x00FF,
+  //.base.freq_min = U2_DOUBLE_TO_FXPT_FREQ(xxx),
+  //.base.freq_max = U2_DOUBLE_TO_FXPT_FREQ(xxx),
+  //.base.freq_step_size = U2_DOUBLE_TO_FXPT_FREQ(xxx),
+  //.base.gain_min = U2_DOUBLE_TO_FXPT_GAIN(xxx),
+  //.base.gain_max = U2_DOUBLE_TO_FXPT_GAIN(xxx),
+  //.base.gain_step_size = U2_DOUBLE_TO_FXPT_GAIN(xxx),
+  .base.is_quadrature = true,
+  .base.i_and_q_swapped = false,
+  .base.spectrum_inverted = false,
+  //.base.lo_offset = U2_DOUBLE_TO_FXPT_FREQ(4e6),
+  .base.init = rfx_init_tx,
+  .base.set_freq = rfx_set_freq,
+  .base.set_gain = rfx_set_gain,
+  .base.set_tx_enable = rfx_set_tx_enable,
+  .base.atr_mask = 0x00E0,
+  .base.atr_txval = MIX_EN, 
+  .base.atr_rxval = ANT_SW,
+  // .base.atr_tx_delay =
+  // .base.atr_rx_delay =
+  .common.DIV2 = 1,
+  .common.CP1 = 7,
+  .common.CP2 = 7,
+  .common.spi_mask = SPI_SS_TX_DB,
+  .common.freq_mult = 2
+};
+
+struct db_rfx_1800_rx db_rfx_1800_rx = {
+  .base.dbid = 0x0034,
+  .base.is_tx = false,
+  .base.output_enables = 0x00E0,
+  .base.used_pins = 0x00FF,
+  //.base.freq_min = U2_DOUBLE_TO_FXPT_FREQ(xxx),
+  //.base.freq_max = U2_DOUBLE_TO_FXPT_FREQ(xxx),
+  //.base.freq_step_size = U2_DOUBLE_TO_FXPT_FREQ(xxx),
+  //.base.gain_min = U2_DOUBLE_TO_FXPT_GAIN(xxx),
+  //.base.gain_max = U2_DOUBLE_TO_FXPT_GAIN(xxx),
+  //.base.gain_step_size = U2_DOUBLE_TO_FXPT_GAIN(xxx),
+  .base.is_quadrature = true,
+  .base.i_and_q_swapped = false,
+  .base.spectrum_inverted = false,
+  //.base.lo_offset = U2_DOUBLE_TO_FXPT_FREQ(4e6),
+  .base.init = rfx_init_rx,
+  .base.set_freq = rfx_set_freq,
+  .base.set_gain = rfx_set_gain,
+  .base.set_tx_enable = 0,
+  .base.atr_mask = 0x00E0,
+  .base.atr_txval = 0,
+  .base.atr_rxval = MIX_EN,
+  // .base.atr_tx_delay =
+  // .base.atr_rx_delay =
+  .common.DIV2 = 0,
+  .common.CP1 = 7,
+  .common.CP2 = 7,
+  .common.spi_mask = SPI_SS_RX_DB,
+  .common.freq_mult = 1
+};
+
+
+struct db_rfx_1800_tx db_rfx_1800_tx = {
+  .base.dbid = 0x0035,
+  .base.is_tx = true,
+  .base.output_enables = 0x00E0,
+  .base.used_pins = 0x00FF,
+  //.base.freq_min = U2_DOUBLE_TO_FXPT_FREQ(xxx),
+  //.base.freq_max = U2_DOUBLE_TO_FXPT_FREQ(xxx),
+  //.base.freq_step_size = U2_DOUBLE_TO_FXPT_FREQ(xxx),
+  //.base.gain_min = U2_DOUBLE_TO_FXPT_GAIN(xxx),
+  //.base.gain_max = U2_DOUBLE_TO_FXPT_GAIN(xxx),
+  //.base.gain_step_size = U2_DOUBLE_TO_FXPT_GAIN(xxx),
+  .base.is_quadrature = true,
+  .base.i_and_q_swapped = false,
+  .base.spectrum_inverted = false,
+  //.base.lo_offset = U2_DOUBLE_TO_FXPT_FREQ(4e6),
+  .base.init = rfx_init_tx,
+  .base.set_freq = rfx_set_freq,
+  .base.set_gain = rfx_set_gain,
+  .base.set_tx_enable = rfx_set_tx_enable,
+  .base.atr_mask = 0x00E0,
+  .base.atr_txval = MIX_EN, 
+  .base.atr_rxval = ANT_SW,
+  // .base.atr_tx_delay =
+  // .base.atr_rx_delay =
+  .common.DIV2 = 0,
+  .common.CP1 = 7,
+  .common.CP2 = 7,
+  .common.spi_mask = SPI_SS_TX_DB,
+  .common.freq_mult = 1
+};
+
+
+struct db_rfx_2400_rx db_rfx_2400_rx = {
+  .base.dbid = 0x0027,
+  .base.is_tx = false,
+  .base.output_enables = 0x00E0,
+  .base.used_pins = 0x00FF,
+  //.base.freq_min = U2_DOUBLE_TO_FXPT_FREQ(xxx),
+  //.base.freq_max = U2_DOUBLE_TO_FXPT_FREQ(xxx),
+  //.base.freq_step_size = U2_DOUBLE_TO_FXPT_FREQ(xxx),
+  //.base.gain_min = U2_DOUBLE_TO_FXPT_GAIN(xxx),
+  //.base.gain_max = U2_DOUBLE_TO_FXPT_GAIN(xxx),
+  //.base.gain_step_size = U2_DOUBLE_TO_FXPT_GAIN(xxx),
+  .base.is_quadrature = true,
+  .base.i_and_q_swapped = false,
+  .base.spectrum_inverted = false,
+  //.base.lo_offset = U2_DOUBLE_TO_FXPT_FREQ(4e6),
+  .base.init = rfx_init_rx,
+  .base.set_freq = rfx_set_freq,
+  .base.set_gain = rfx_set_gain,
+  .base.set_tx_enable = 0,
+  .base.atr_mask = 0x00E0,
+  .base.atr_txval = 0,
+  .base.atr_rxval = MIX_EN,
+  // .base.atr_tx_delay =
+  // .base.atr_rx_delay =
+  .common.DIV2 = 0,
+  .common.CP1 = 7,
+  .common.CP2 = 7,
+  .common.spi_mask = SPI_SS_RX_DB,
+  .common.freq_mult = 1
+};
+
+
+struct db_rfx_2400_tx db_rfx_2400_tx = {
+  .base.dbid = 0x002b,
+  .base.is_tx = true,
+  .base.output_enables = 0x00E0,
+  .base.used_pins = 0x00FF,
+  //.base.freq_min = U2_DOUBLE_TO_FXPT_FREQ(xxx),
+  //.base.freq_max = U2_DOUBLE_TO_FXPT_FREQ(xxx),
+  //.base.freq_step_size = U2_DOUBLE_TO_FXPT_FREQ(xxx),
+  //.base.gain_min = U2_DOUBLE_TO_FXPT_GAIN(xxx),
+  //.base.gain_max = U2_DOUBLE_TO_FXPT_GAIN(xxx),
+  //.base.gain_step_size = U2_DOUBLE_TO_FXPT_GAIN(xxx),
+  .base.is_quadrature = true,
+  .base.i_and_q_swapped = false,
+  .base.spectrum_inverted = false,
+  //.base.lo_offset = U2_DOUBLE_TO_FXPT_FREQ(4e6),
+  .base.init = rfx_init_tx,
+  .base.set_freq = rfx_set_freq,
+  .base.set_gain = rfx_set_gain,
+  .base.set_tx_enable = rfx_set_tx_enable,
+  .base.atr_mask = 0x00E0,
+  .base.atr_txval = MIX_EN, 
+  .base.atr_rxval = ANT_SW,
+  // .base.atr_tx_delay =
+  // .base.atr_rx_delay =
+  .common.DIV2 = 0,
+  .common.CP1 = 7,
+  .common.CP2 = 7,
+  .common.spi_mask = SPI_SS_TX_DB,
+  .common.freq_mult = 1
+};
+
+
 bool
 rfx_init_tx(struct db_base *dbb)
 {
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