[Commit-gnuradio] r8557 - usrp2/trunk/fpga/sdr_lib

[matt]

Author: matt
Date: 2008-06-05 15:58:52 -0600 (Thu, 05 Jun 2008)
New Revision: 8557

Modified:
   usrp2/trunk/fpga/sdr_lib/small_hb_dec.v
   usrp2/trunk/fpga/sdr_lib/small_hb_dec_tb.v
Log:
missed a stupid bug


Modified: usrp2/trunk/fpga/sdr_lib/small_hb_dec.v
===================================================================
--- usrp2/trunk/fpga/sdr_lib/small_hb_dec.v     2008-06-05 21:00:28 UTC (rev 
8556)
+++ usrp2/trunk/fpga/sdr_lib/small_hb_dec.v     2008-06-05 21:58:52 UTC (rev 
8557)
@@ -47,11 +47,15 @@
        end
 
    reg [17:0] sum_a, sum_b, middle, middle_d1;
+   wire [17:0] sum_a_unreg, sum_b_unreg;
+   add2 #(.WIDTH(18)) add2_a (.in1(data_in_d1),.in2(d6),.sum(sum_a_unreg));
+   add2 #(.WIDTH(18)) add2_b (.in1(d2),.in2(d4),.sum(sum_b_unreg));
+   
    always @(posedge clk)
      if(go)
        begin
-         sum_a <= data_in_d1 + d6;
-         sum_b <= d2 + d4;
+         sum_a <= sum_a_unreg;
+         sum_b <= sum_b_unreg;
          middle <= d3;
        end
 
@@ -69,7 +73,7 @@
      if(rst)
        accum <= 0;
      else if(go_d2)
-       accum <= {middle_d1[17],middle_d1,17'd0} + {prod};
+       accum <= {middle_d1[17],middle_d1[17],middle_d1,16'd0} + {prod};
      else if(go_d3)
        accum <= accum + {prod};
    

Modified: usrp2/trunk/fpga/sdr_lib/small_hb_dec_tb.v
===================================================================
--- usrp2/trunk/fpga/sdr_lib/small_hb_dec_tb.v  2008-06-05 21:00:28 UTC (rev 
8556)
+++ usrp2/trunk/fpga/sdr_lib/small_hb_dec_tb.v  2008-06-05 21:58:52 UTC (rev 
8557)
@@ -1,8 +1,8 @@
-module small_hb_dec_tb( ) ;
+module hb_dec_tb( ) ;
    
     // Parameters for instantiation
-    parameter               clocks  = 1 ; // Number of clocks per input
-    parameter               decim   = 0 ; // Sets the filter to decimate
+    parameter               clocks  = 9'd2 ; // Number of clocks per input
+    parameter               decim   = 1 ; // Sets the filter to decimate
     parameter               rate    = 2 ; // Sets the decimation rate
 
     reg                     clock ;
@@ -15,8 +15,8 @@
 
    initial
      begin
-       $dumpfile("small_hb_dec_tb.vcd");
-       $dumpvars(0,small_hb_dec_tb);
+       $dumpfile("hb_dec_tb.vcd");
+       $dumpvars(0,hb_dec_tb);
      end
    
     // Setup the clock
@@ -54,6 +54,12 @@
    
     integer i, ri, ro, infile, outfile ;
 
+   always @(posedge clock)
+     begin
+       if(strobe_out)
+         $display(data_out);
+     end
+   
     // Setup file IO
     initial begin
         infile = $fopen("input.dat","r") ;
@@ -107,27 +113,28 @@
         else
             $display( "PASSED: Simulation successful" ) ;
 
-        $stop ;
+        $finish ;
     end
 
-    // Output comparison of simulated values versus known good values
-    always @ (posedge clock) begin
-        if( reset )
-            endofsim <= 1'b0 ;
-        else begin
-            if( !$feof(outfile) ) begin
-                if( strobe_out ) begin
-                    ro = $fscanf( outfile, "%d\n", compare ) ;
-                    if( compare != data_out ) begin
-                        $display( "%t: %d != %d", $realtime, data_out, compare 
) ;
-                        noe = noe + 1 ;
-                    end
-                end
-            end else begin
-                // Signal end of simulation when no more outputs
-                endofsim <= 1'b1 ;
+   // Output comparison of simulated values versus known good values
+   always @ (posedge clock) begin
+      if( reset )
+        endofsim <= 1'b0 ;
+      else begin
+         if( !$feof(outfile) ) begin
+            if( strobe_out ) begin
+               ro = $fscanf( outfile, "%d\n", compare ) ;
+               if( compare != data_out ) begin
+                  //$display( "%t: %d != %d", $realtime, data_out, compare ) ;
+                  noe = noe + 1 ;
+               end
             end
-        end
-    end     
+         end else begin
+            // Signal end of simulation when no more outputs
+            endofsim <= 1'b1 ;
+         end
+      end
+   end     
 
-endmodule
+endmodule // hb_dec_tb
+