[Commit-gnuradio] r9096 - usrp2/trunk/fpga/sdr_lib

[matt]

Author: matt
Date: 2008-07-31 20:21:43 -0600 (Thu, 31 Jul 2008)
New Revision: 9096

Modified:
   usrp2/trunk/fpga/sdr_lib/tx_control.v
Log:
fixed major bug in xfer_state state machine which would cause it to refill with 
junk when there was an underflow.
Also added fifo level outputs and adapted to the new interface for the fifo 
full/empty connections.


Modified: usrp2/trunk/fpga/sdr_lib/tx_control.v
===================================================================
--- usrp2/trunk/fpga/sdr_lib/tx_control.v       2008-08-01 02:19:57 UTC (rev 
9095)
+++ usrp2/trunk/fpga/sdr_lib/tx_control.v       2008-08-01 02:21:43 UTC (rev 
9096)
@@ -22,6 +22,12 @@
      output run,
      input strobe,
 
+     // FIFO Levels
+     output [15:0] fifo_occupied,
+     output fifo_full,
+     output fifo_empty,
+
+     // Debug
      output [31:0] debug
      );
 
@@ -40,23 +46,26 @@
    always @(posedge clk)
      if(rst)
        xfer_state <= XFER_IDLE;
-     else 
-       case(xfer_state)
-        XFER_IDLE :
-          if(rd_sop_i)
-            xfer_state <= XFER_1;
-        XFER_1 :
-          begin
-             xfer_state <= XFER_2;
-             held_flags <= rd_dat_i[2:0];
-          end
-        XFER_2 :
-          if(~full_ctrl)
-            xfer_state <= XFER_DATA;
-        XFER_DATA :
-          if(rd_eop_i & ~full_data)
-            xfer_state <= XFER_IDLE;
-       endcase // case(xfer_state)
+     else
+       if(clear_state)
+        xfer_state <= XFER_IDLE;
+       else
+        case(xfer_state)
+          XFER_IDLE :
+            if(rd_sop_i)
+              xfer_state <= XFER_1;
+          XFER_1 :
+            begin
+               xfer_state <= XFER_2;
+               held_flags <= rd_dat_i[2:0];
+            end
+          XFER_2 :
+            if(~full_ctrl)
+              xfer_state <= XFER_DATA;
+          XFER_DATA :
+            if(rd_eop_i & ~full_data)
+              xfer_state <= XFER_IDLE;
+        endcase // case(xfer_state)
    
    assign write_data = (xfer_state == XFER_DATA) & ~full_data;
    assign write_ctrl = (xfer_state == XFER_2) & ~full_ctrl;
@@ -68,16 +77,21 @@
    wire [31:0] data_o;
    wire        sop_o, eop_o, eob, sob, send_imm;
    wire [31:0] sendtime;
+   wire [4:0]  occ_ctrl;
    
    cascadefifo2 #(.WIDTH(34),.SIZE(FIFOSIZE)) txctrlfifo
      (.clk(clk),.rst(rst),.clear(clear_state),
       .datain({rd_sop_i,rd_eop_i,rd_dat_i}), .write(write_data), 
.full(full_data),
-      .dataout({sop_o,eop_o,data_o}), .read(read_data), .empty(empty_data) );
+      .dataout({sop_o,eop_o,data_o}), .read(read_data), .empty(empty_data),
+      .space(), .occupied(fifo_occupied) );
+   assign      fifo_full = full_data;
+   assign      fifo_empty = empty_data;
 
    shortfifo #(.WIDTH(35)) ctrlfifo
      (.clk(clk),.rst(rst),.clear(clear_state),
       .datain({held_flags[2:0],rd_dat_i}), .write(write_ctrl), 
.full(full_ctrl),
-      .dataout({send_imm,sob,eob,sendtime}), .read(read_ctrl), 
.empty(empty_ctrl) );
+      .dataout({send_imm,sob,eob,sendtime}), .read(read_ctrl), 
.empty(empty_ctrl),
+      .space(), .occupied(occ_ctrl) );
 
    // Internal FIFO to DSP interface
    reg [2:0]   ibs_state;
@@ -139,8 +153,8 @@
 
    assign      sample = data_o;
 
-   assign      debug = { 16'd0,
-                        {eop_o, eob, send_imm ,too_late, go_now, 
ibs_state[2:0] }, 
-                        empty_data, empty_ctrl, read_data, read_ctrl, strobe, 
clear_state, run, underrun};
+   assign      debug = { {16'b0},
+                        { read_data, write_data, read_ctrl, write_ctrl, 
xfer_state[1:0],full_ctrl,empty_ctrl },
+                        { occ_ctrl, eop_o, clear_state, underrun} };
    
 endmodule // tx_control