[Commit-gnuradio] r9807 - in gnuradio/trunk/usrp2: firmware/lib fpga/sdr_lib

[matt]

Author: matt
Date: 2008-10-18 17:33:12 -0600 (Sat, 18 Oct 2008)
New Revision: 9807

Modified:
   gnuradio/trunk/usrp2/firmware/lib/memory_map.h
   gnuradio/trunk/usrp2/fpga/sdr_lib/dsp_core_tx.v
Log:
added in mux for DACs


Modified: gnuradio/trunk/usrp2/firmware/lib/memory_map.h
===================================================================
--- gnuradio/trunk/usrp2/firmware/lib/memory_map.h      2008-10-18 19:57:08 UTC 
(rev 9806)
+++ gnuradio/trunk/usrp2/firmware/lib/memory_map.h      2008-10-18 23:33:12 UTC 
(rev 9807)
@@ -407,11 +407,12 @@
    *   1   DUC 0 Q
    *   2   DUC 1 I
    *   3   DUC 1 Q
-   *
+   *   F   All Zeros
+   *   
    * The default value is 0x10
    * </pre>
    */
-  //volatile uint32_t  tx_mux;         // FIXME this register is currently 
unimplemented
+  volatile uint32_t    tx_mux;         // FIXME this register is currently 
unimplemented
 
 } dsp_tx_regs_t;
   

Modified: gnuradio/trunk/usrp2/fpga/sdr_lib/dsp_core_tx.v
===================================================================
--- gnuradio/trunk/usrp2/fpga/sdr_lib/dsp_core_tx.v     2008-10-18 19:57:08 UTC 
(rev 9806)
+++ gnuradio/trunk/usrp2/fpga/sdr_lib/dsp_core_tx.v     2008-10-18 23:33:12 UTC 
(rev 9807)
@@ -19,7 +19,7 @@
    wire [31:0] phase_inc;
    reg [31:0]  phase;
    wire [7:0]  interp_rate;
-
+   wire [3:0]  dacmux_a, dacmux_b;
    wire        enable_hb1, enable_hb2;
 
    setting_reg #(.my_addr(`DSP_CORE_TX_BASE+0)) sr_0
@@ -34,6 +34,10 @@
      (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
       .in(set_data),.out({enable_hb1, enable_hb2, interp_rate}),.changed());
 
+   setting_reg #(.my_addr(`DSP_CORE_TX_BASE+4)) sr_4
+     (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
+      .in(set_data),.out({dacmux_b,dacmux_a}),.changed());
+
    // Strobes are all now delayed by 1 cycle for timing reasons
    wire        strobe_cic_pre, strobe_hb1_pre, strobe_hb2_pre;
    reg                strobe_cic = 1;
@@ -122,11 +126,19 @@
       );
    
    always @(posedge clk)
-     dac_a <= prod_i[28:13];
+     case(dacmux_a)
+       0 : dac_a <= prod_i[28:13];
+       1 : dac_a <= prod_q[28:13];
+       default : dac_a <= 0;
+     endcase // case(dacmux_a)
    
    always @(posedge clk)
-     dac_b <= prod_q[28:13];
-
+     case(dacmux_b)
+       0 : dac_b <= prod_i[28:13];
+       1 : dac_b <= prod_q[28:13];
+       default : dac_b <= 0;
+     endcase // case(dacmux_b)
+   
    assign      debug = {strobe_cic, strobe_hb1, strobe_hb2,run};
 
 endmodule // dsp_core