Re: [Gnucap-devel] verilog-a(ms) roadmap?

[al davis]

On Monday 14 May 2007, Dan McMahill wrote:
> Is there a plan to produce a verilog-a capable gnucap on the
> way to a full verilog-ams version?  
yes.

> Or is verilog-a 
> considered the stopping point?
no,

> I'm curious, will the digital portion of verilog-ams fit into
> gnucap's existing framework or will you need to develop a new
> kernel for the verilog-hdl part? 

It fits with the existing framework.

> Or is it possible to 
> integrate portions of icarus verilog for this?

That too.

The existing kernel is a mixed-mode kernel.  It already 
implements the concept of a "connectmodule", but with the wrong 
syntax.  It always has done this.  I think gnucap is the first 
simulator ever to correctly implement the concept of 
a "connectmodule".

The core will support the structural subset, interpreted, with 
very limited behavioral modeling.  Full behavioral support will 
need to be compiled for speed.

The model compiler generates something that eventually turns to 
a ".so" file that can be used as a plug-in.  The plan is to 
rework it to take Verilog-AMS as the source language instead of 
the existing ".model" files.  Eventually, it should evolve to 
the whole language.

There are other ways to generate model plugins, including 
wrapping Spice C models.  There will be more other ways too, 
probably also including Icarus Verilog eventually.  I think 
ADMS works now, but have not tested it.  I also think it should 
be easy to make a wrapper for XSPICE codemodels, but I am not 
sure if it is worth the effort.

Current status ....   
Now working on language plugins.  I tripped a few times, had to 
back up and rework a few times.  I think I have the right path 
now.  The Spice code (code to read and write Spice format) will 
require more rework than I expected.  Spectre, Qucs, VHDL 
formats should be easy after getting the system in place.  The 
hard part is getting the system in place.

Not much got done in April.  I was away most of the month.