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possible bug/misbehaviour in builtin mos


From: Felix Salfelder
Subject: possible bug/misbehaviour in builtin mos
Date: Wed, 4 Jan 2023 00:15:15 +0100

I found a situation, where node comparison does not behave as intended
at least not as expected. See test in node_bug branch.

The test is the mos inverter from d_mos1.inv1.ckt but with the n-type
fet in a subcircuit.

.subckt n 1 2 3 4
Mn1 1 2 3 4 NMOS W=8e-6 L=600e-9
.ends

X1 3 2 0 0 n
* was: Mn1 3 2 0 0 NMOS W=8e-6 L=600e-9

Unlike in the original Mn1, in X1.Mn1 a redundant diode between source
and drain is instanciated.

The responsible comparison is _n[n_b].n_() == _n[n_s].n_(), see
DEV_BUILT_IN_MOS::expand. It comes directly from the .model. I wonder if
it should be t_, not n_. But then, t_ looks redundant. Maybe some deeper
changes are required and/or pending...?

thanks
felix



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