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How to disable "_i" insertion on signals in emacs VHDL mode
From: |
chris . plachta |
Subject: |
How to disable "_i" insertion on signals in emacs VHDL mode |
Date: |
31 Jan 2007 11:58:56 -0800 |
User-agent: |
G2/1.0 |
Hi,
Does anyone know how to disable the automatic insertion of "_i" on
signals that are connect to a instance port map?
For example, when I use the vhdl-paste-port-instance command on a
model with the ports called "rst_l" and "clk", it gives me this:
instance: clk_model
port map (
rst_l => rst_l_i,
clk => clk_i);
I want to get rid of the "_i" convention and use identical names for
the port and the signal.
Thanks in advance...
Chris
- How to disable "_i" insertion on signals in emacs VHDL mode,
chris . plachta <=