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Re: confused by emacs verilog mode


From: chenyong20000
Subject: Re: confused by emacs verilog mode
Date: Sun, 25 May 2014 19:20:58 -0700 (PDT)
User-agent: G2/1.0

在 2014年5月26日星期一UTC+8上午9时05分51秒,chenyo...@gmail.com写道:
> 在 2014年5月26日星期一UTC+8上午3时36分00秒,Stefan Monnier写道:
> 
> > >> I'm trying to use emacs verilog mode for vi. I have a piece of code
> 
> > 
> 
> > >> like this:
> 
> > 
> 
> > [...]
> 

finally I found the root reason. Thanks.
> > 
> 
> > >> what confused me is that after generate code, it seems like this:
> 
> > 
> 
> > [...]
> 
> > 
> 
> > >> you can find from these code that the dataout0_r_entry_xxx has been
> 
> > 
> 
> > >> changed from dataout0 to dataout1. I don't know how this happens and
> 
> > 
> 
> > >> how can i get right code. Can anybody help me? thanks.
> 
> > 
> 
> > 
> 
> > 
> 
> > You say "after generate code", but I have no idea what that step
> 
> > 
> 
> > refers to.  What makes you think this has to do with Emacs?
> 
> > 
> 
> > 
> 
> > 
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> > 
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> > 
> 
> >         Stefan
> 
> 
> 
> Hi Stefan,
> 
> in fact the editor is vi, but company IT has embedded some scripts so that 
> the vi could use those features for emacs. The vi works fine with other 
> files, but failed on these pieces of code. Why do you think this has no 
> relation to emacs?Thanks.



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