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Re: gmake: how to avoid $$@ usage?


From: Ernest
Subject: Re: gmake: how to avoid $$@ usage?
Date: Wed, 02 Mar 2005 14:31:07 -0600
User-agent: Xnews/5.04.25

"Paul D. Smith" <psmith@gnu.org> wrote in 
vpdrsm3fxghd.fsf@lemming.engeast.baynetworks.com:">news:vpdrsm3fxghd.fsf@lemming.engeast.baynetworks.com:

> If you're restricted to the capabilities of clearmake -C gnu, then you
> have no chance.  You'll have to generate makefiles.  And, clearmake
> doesn't support GNU make's auto-re-exec method so you'll have to
> actually do this by invoking clearmake twice, explicitly.

Actually, I think I found a way today to do this with $(shell) so I don't 
have to re-invoke make (which wouldn't work since the sub-make wouldn't 
have all the currently defined vars, and there are a LOT of them).  For 
example:

################################################
# kludge to mimic an $(if)-like conditional for var defintion
_defined_ = $(subst 000,${${IF}},$(subst 010,${${ELSE}},0$(words 
$(findstring undefined,$(origin ${VAR})))0))

# this doesn't include case #3, but that's academic to add
_OFILES_ = $(foreach VAR,${prog}_OFILES,$(foreach IF,${prog}_OFILES,
$(foreach ELSE,OFILES,${_defined_})))

# now create makefile2 at parse time
dummy := $(foreach prog,${PROGRAMS},$(shell echo ${prog} : ${_OFILES_} >>
makefile2))

# include it, so it's as if we have the targ:prereq lists explict
include makefile2

${PROGRAMS} :  # prereq's have already been set in makefile2
        # commands here
################################################

So makefile2 will contain simple targ:prereq lines (no commands) for all 
words listed in PROGRAMS.  e.g.,

foo.exe : a.obj b.obj c.obj
bar.exe : d.obj e.obj

Necessity is the mother of invention, right?  8^)  Whew!

Cheers,
Ernest


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