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Makefile Question.

From: Jaemin Kang
Subject: Makefile Question.
Date: 15 Jul 2005 04:10:36 -0700
User-agent: G2/0.2

I'm trying to compile my source files on Linux(Redhat 9).

I already have the makefile to compile my source files on Win32
(I used Microsoft's 'nmake')

so I changed the makefile a little.

But I got an error message.

make: *** No rule to make target 'Object.o' needed by 'all'. Stop.

This is my makefile

OUTPUT_DIR          = ..\..\..\objs
THERON_SRC_DIR      = ..\..\..\src
ARM_CC              = arm-elf-gcc
OBJ_CMD             = -o
OUT                 = -c
OPT                 = -O2
CFLAGS              = $(OUT) $(OPT)

SRC_FILE = $(@F:.o=.c)

.SUFFIXES : .o .c

{$(THERON_SRC_DIR)}.c.o :
        @echo -----------------------------------------------------
        @echo OBJECT $(@F)
        $(ARM_CC) $(CFLAGS) $(OBJ_FILE) $(SRC_FILE)
        @echo -----------------------------------------------------

THERON_OBJS            =                \
                         Object.o       \
                         File.o         \
                         AnsiFile.o     \
                         BrewFile.o     \
                         Memory.o       \
                         AnsiMemory.o   \
                         BrewMemory.o   \

all : $(THERON_OBJS)

clean :
        @echo CLEAN
        -rm /f $(THERON_OBJS)

It seems that The GNU make doen't understand below line.

'{$(THERON_SRC_DIR)}.c.o :'

My source files and the makefile are in different directory.

Can anyone tell me how to handle this?

Thanks in advance.

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