automake moves assignment around (out of Makefile conditional)

[Daniel Kabs]

Hello,

I'am a beginner regarding automake, so please bear with me if I am 
ignorant to the usual automake practices: I want to include some code in 
Makefile.am so that if finally ends up verbatim in the Makefile. Example:

ifeq "$(strip $(TESTDIR))" ""
 TESTDIR=/tmp/testdir
endif

According to

http://sources.redhat.com/automake/automake.html#General-Operation

by running automake "The variable definitions and rules in the 
Makefile.am are copied verbatim into the generated file" (i.e. Makefile.im)

Brilliant, the task should be foolproof, I thought. But automake proved 
me wrong!

Automake emitted an error "Makefile.am:47: endif without if". No 
problem, this can be resolved by indenting the above code with one space.

But it also moved the assignment out of the if-endif clause to the top 
of Makefile.in.

Why is this and how can I avoid this easily?

Cheers
Daniel
Germany
--
Granted, CVS does not handle binary files as well as it handles
mergeable text files.  But even with CVS's handicaps and limitations
WRT binary, CVS is still orders of magnitude better than manually
maintaining versions of files in a directory.(Jim Hyslop on info-cvs)