more make questions

[James]

$ cat makefile
all: T
define MK
$(1): VAR=$(2)
$(1): S
        @echo $$@ $$(VAR)
endef
$(eval $(call MK,T,abc))
S:
        @echo $@ $(VAR)
ifeq ($(VAR),)
        @echo VAR is an empty string
else
        @echo VAR=$(VAR)
endif

$ make-3.81beta3
S abc
VAR is an empty string
T abc

But, I wish to see
S abc
VAR=abc
T abe

However, if makefile is modified as
all: T
VAR=12345
define MK
...
then, I get
S abc
VAR=abc
T abc

What is going on?
James