Re: $(wildcard) with Make

[Paul D. Smith]

%% ncmadcity@gmail.com writes:

  n> I have a makefile that builds a compiler, then compiles a number of
  n> test programs to instructions for Jasmin (assembler for the JVM), then
  n> assembles them by calling Jasmin. The makefile currently does something
  n> like this:

  n> $(foreach f, $(tests), java Compile $f &&) echo "Compiled tests
  n> successfully"
  n> $(foreach f, $(wildcard *.j), jasmin $f &&) echo "Assembled tests
  n> successfully"

  n> The crucial problem here is with $(wildcard *.j), which apparently
  n> expands to an empty string unless the matching files are present in the
  n> directory before Make is invoked (not before that line is executed, as
  n> I expected). I can run make a 2nd time to get around the problem, but
  n> obviously this is not ideal. Is anyone out there a Make guru who can
  n> suggest a good way for me to get this behavior without ugly kludges
  n> (and without listing all the input and target files in the makefile)?

Use the shell's loop, not make's loop: then you can use the shell's
wildcard management:

    sometarget:
        for f in *.j; do jasmin $$f || exit $$?; done
        echo "Assembled tests successfully"

-- 
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 Paul D. Smith <psmith@gnu.org>          Find some GNU make tips at:
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 "Please remain calm...I may be mad, but I am a professional." --Mad Scientist