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Help with GNU Makefile

From: g35rider
Subject: Help with GNU Makefile
Date: 21 Jun 2006 18:59:37 -0700
User-agent: G2/0.2

   I have always been afraid of makefiles and I was given a generic
makefile to use and have been using that. Now I dont like it much since
it doesnt cover everything I would like it to.

I am trying to make a generic makefile, in an effort to understand the
makefile itself.

I have written a makefile to make libraries.


TOPDIR= ../..

CC= gcc
CPP= g++
MKLIB= ar rvu
RM= rm -rf

INC_CFLAGS= -I/usr/include/mysql++ -I$(TOPDIR)/cncpbaseclass
-I/usr/include/mysql -I$(TOPDIR)/oammsg
-I$(TOPDIR)/neoamcomm -I../util_lib -I$(TOPDIR)/util


#This is where you put the name of the library you are creating
OUT_LIB= libdbaccess.a
#This is the directory where the library will be put

SRCS= myprog1.cpp myprog2.cpp
INCLUDES= myheader1.h ../include/myheader2.h

#OBJS= $(SRCS:%.cpp=%.o)

all: $(OUT_LIB_DIR)/$(OUT_LIB)

        $(COMPILE) $(CFLAGS) -c $?
        $(MKLIB) $(OUT_LIB_DIR)/$(OUT_LIB) $(OBJS)
        $(RM) $(OBJS)

        $(RM) $(OUT_LIB_DIR)/$(OUT_LIB) *~* *#* *.o


This seems to work just fine for source file changes. But I cant seem
to figure out how to add header file dependencies to it? The reason I
didnt put the OBJ file rule in the makefile is because I dont want the
.o files, I create an .a file out of all the .o's so I delete the .o's.
So I skipped that step, thats y compiling and archiving are in one

Now if I add $(INCLUDES) in the OUT_LIB target then if I change the
header file, it tries to compile it, and I can see y it does that. I
want when the header file is changed it should remake all the $(SRCS)
files or a subset of those that depend on it.

How can I achieve this?


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