makefile - define targets, dependencies in a variable

[Steve Calfee]

Hi, maybe Paul or someone can help on this.

I have a pretty large build of multiple source files being built into
libraries. In order to minimize duplicate, identical makefiles, I
include them with new names defined to do the same thing ie:

#list of packages to be built into libraries
<whole bunch of snips>
#sample
PACKAGE_NAME := usb_hid/host/base
$(PACKAGE_NAME)_LIB := nu_usbh_hid.lib
include $(MAKEFILE_PATH)/makefile_pattern.mk
include $(MAKEFILE_PATH)/makefile_pattern_2.mk

....

And these two included files glob the sources, build vpath etc. It
works really well, but it seems like I should be able to do at least
the simpler one as a variable rather than an included file.

makefile_pattern_2.mk is:
$($(PACKAGE_NAME)_LIB) : $($($(PACKAGE_NAME)_LIB)_OBJS)
        @echo     $($(PACKAGE_NAME)_LIB)_OBJS
        $(AR) $(ARFLAGS) $@ $(addprefix $(OBJ_DIR)/,$(notdir $?))

What I would like to do is:
XXXX = cmdslikeabove

and then use them in my makefile in place of the include. As:
$(cmdslikeabove)

So the question is can I define rules in a variable, and maybe give an
example?

Thanks.