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20 Apr 2007 11:31:52 -0700
I'm trying to do the following: I want to populate the contents of a
variable with the result of a compilation step within the makefile.
that is, I want to instruct make to first execute some commands, and
then populate the names of some variables and then execute some more
commands, based on the contents of the new information stored in the
Here is what I have currently in my makefile:
MODULES = $(SYM_OBJS)
@echo 'building the AST...'
cd $(ASTPATH) && make $@
@echo 'building the symtabs...'
cd $(SYMPATH) && make $@
@echo 'building the visitors...'
cd $(VISITORPATH) && make $@
$(YACC) $(YACC_FLAGS) $(YACC_IN) # => $(PROJ_NAME).tab.c + $
$(LEX) $(LEX_FLAGS) $(LEX_IN) # => lex.yy.c
$(CC) -c $(CPPFLAGS) $(LEX_OUT) -o $(LEX_OUT_COMP) # =>
$(CC) -c $(CPPFLAGS) $(YACC_OUT) -o $(YACC_OUT_COMP) # =>
@echo ' za main program ...'
$(CC) $(YACC_OUT_COMP) $(LEX_OUT_COMP) $(OBJS) $(LEX_LIB) $
@echo 'Done BUILD!'
In $(ASTPATH) , $(SYMPATH) and $(VISITORPATH) , I have separate
makefiles which build me objects. Then, I want that thes object names
be picked up and stored in $(MODULES) automatically, so that they will
be finally linked into the main executable.
All I could find in man make was .SECONDEXPANSION but that isn't
helpful to me, because the compilation step must first execute, in
order to populate MODULES with the right info.
- [make]wildcard question,