Re: [Help-gnucap] Time step control

[a r]

On Feb 18, 2008 2:28 AM, al davis <address@hidden> wrote:
>
> In tests I have run, it is far from perfect, but on the average
> appears to be somewhat better than Spice (3f5 or NG).  I have
> seen several cases where Spice gives you believable but
> incorrect results.  On those same cases, gnucap either
> explicitly fails, gives a warning, or works correctly.

What I expect from good time step control is (conceptually) simple:
1. Adjust time step so that local truncation error is constant
(slightly less than specified value),
2. Limit time step to such value that numerical instability will not occur.

> Can you send me the one that is giving you trouble?

I have partially solved the problem with my circuit (using trap method
and larger dtmin). Nevertheless, I'll try to prepare a netlist that
exposes the problem for a smaller circuit and post it here. BTW, my
circuit is nothing special - it's a clocked CMOS transistor level
logic driving some interconnection models.

> > Problems:
> >
> > 1. Using euler method:
[...]
> You changed ITL4 from 20 to 10.  This is not a good idea.

Well, this was the only way I could come up with to make Gnucap
decrease time step at "difficult parts". Later you wrote:

> bsim_310 uses generates only truncation error time step control,
> which is disabled when you use Euler.

which looks like a direct reason of this problem. I would much more
prefer to have the time step control enabled for _any_ kind of
transient analysis. Constant time step is a serious limitation for me.

> There are plans to add threshold crossing time step control to
> the spice models, but it isn't done yet.
[...]
> s11 (0 0 n1 n2) control_hack
> .model control_hack sw vt=5
> (if you want an event when the voltage crosses 5)

That's interesting. I don't need it for my simulations but I can
imagine such possibility would be useful for some kind of a
measurement language extension.

> > 2. Using trap method:
[...]
> Try increasing dtmin, and tightening chgtol and trtol.  Set
> trtol=1.

Thanks. Increasing dtmin to 1e-12 (this is enough for my circuit)
helped a lot. My current options are:

.option method=trap dtmin=1e-12 abstol=1e-13 vntol=1e-7 chgtol=1e-15
reltol=1e-4 trtol=0.1

I _still_ can see quite a lot of numerical ringing but its amplitude
is now small enough so I can ignore it (and frequency is low enough so
it does not slow down the simulation). I think the threshold between
trap and euler methods for "storage elements" (strays etc.) should be
placed slightly higher than dtmin (say 2~3 * dtmin). It looks for me
that currently the minimum time step is always a bit too large for
those strays that have passed just under dtmin threshold, hence the
numerical ringing.

Thanks,

-r.