In your schematic, you need to rename your LM317 from U1 to X1 .
Spice expects that all subckt components' reference designators will
start with 'X'. I think there is a gschem attribute which will rename
the part from U... to X... during spice netlist generation, but I
don't remember what attribute that is. The easiest thing is to just
change the name in the schematic.
On Tue, Jul 6, 2010 at 4:46 PM, Mogliii<address@hidden> wrote:
OK, I got a bit closer to my aim.
I found this very helpful page: http://www.brorson.com/gEDA/SPICE/t1.html
Following this I made the following schematic:
http://users.ecs.soton.ac.uk/mets09r/test3.sch
I copied the spice model I found here [1] into a subckt file
http://users.ecs.soton.ac.uk/mets09r/LM317.subckt
and gave the LM317 the following attributes:
device = LM317 (apparently not necessary)
refdes = U1
value = LM317 (exactly the same as the .SUBCKT LM317 1 2 3 in
spice file)
file = LM317.subckt (file with spice model is located in same
directory as sch file)
Now when I load it in gspiceui the netlist finds the spicefile and netlists
all. But when I do the simulation I get the following console output:
Gnucap 0.35
The Gnu Circuit Analysis Package
Never trust any version less than 1.0
Copyright 1982-2006, Albert Davis
Gnucap comes with ABSOLUTELY NO WARRANTY
This is free software, and you are welcome
to redistribute it under certain conditions
according to the GNU General Public License.
See the file "COPYING" for details.
**************************************************************
U1 3 2 1 LM317
^ ? need 1 more nodes
@@#
@@@incomplete:d_logic.cc:73:parse_spice
U1 3 2 1 LM317
^ ? need more nodes
U1 3 2 1 LM317
^ ? need and,nand,or,nor,xor,xnor,inv
J1 1 3 4 JN
^ ? illegal type
.MODEL JN NJF(BETA=1E-4 VTO=-7)
^ ? not implemented
model is not a logic family (LOGIC)
The J1 seems to be the problem?
Now my questions:
1) Do I have to rewrite the spice model to work with gnucap?
2) gEDA includes the LM317 as symbol, but apparently no spice model? Is
this correct?
I appreciate your help in advance
[1]
http://groups.google.com/group/sci.electronics.cad/browse_frm/thread/fbf84f10d86a4d23/e66bf3354362d541?q=LM317+spice+model&rnum=3#e66bf3354362d541
On 07/05/2010 08:48 AM, Mogliii wrote:
Since attachments seem not to be allowed on this mailinglist :(( (compare
my previous email) so I uploaded them.
1) the spicelib thing has been already resolved. Use scones instead of
make.
3) Schematics
http://users.ecs.soton.ac.uk/mets09r/current-source.sch
Explanation of circuit
http://users.ecs.soton.ac.uk/mets09r/lm317.png
Any help appreciated
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