Please Help!- I have a problem using make ( variable "$*")

[Kang Sujin-W19218]

Hello.

I am Sujin,Kang in Seoul, Korea.
I am a Software engineer in Motorola Korea Technology Center.

I did a build using gnu make, perl script and arm compiler.
We have no problem in DOS mode but in UNIX....^^;;;;;;

The problem is concerned with the variable "$*";
For example,

file : 
*****a.min*****************************************************************************
$(TARGETDIR)/%.o %.o: %.c
        @echo -----------------------------------------------------------------
        @echo OBJECT $@
        @echo $@ $< $* $?
        $(CC) $(CFLAGS) $(DMSS_CFLAGS) $(MSG_FILE) $(OBJ_CMD) $@ $*.c
        @echo $@ $< $*
        @echo ----------------------------------------------------------------
***********************************************************************************************
a.min is called from a perl script which is called from a main make file.
The echo results are 
% <= surfcoei/bit_
***********************************************************************************************
 echo -----------------------------------------------------------------
 echo OBJECT surfcoei/bit_.o
 echo surfcoei/bit_.o surfcoei/bit_.c bit_ surfcoei/bit_.c
                                                   ^^^^^ this part is the 
problem....
 .........
 (omission)
 ........
************************************************************************************************
I think and I know that variable  "$*" is the base name of target and the 
target minus suffix in implicit rule.
Am I wrong?
If so, I think the echo result has to be not bit_ but surfcoei/bit_. Doesn't it?

What is problem?
I have no idea until now....
please help me and answer it to me.
Thank you for your help and your concern.
and thank you for reading my mail.

bye.

Best Regards,

   Sujin.Kang