Variables to represent pre-requisites

[Nalinaksh Pai]

Folks,

I need your help for the following case.

The makefile is as shown:
################
foo_var1 = a_var1.o
foo_var2 = a_var2.o

foo_%_new: $(foo_%) c_%.o
        echo $^

a_var1.o:
a_var2.o:
c_var1.o:
c_var2.o:
################

When I fire make as shown, the output is 

#] make foo_var1_new
echo c_var1.o
c_var1.o

Now, I was expecting echo to print the pre-req as
a_var1.o c_var1.o

i.e I was expecting
$(foo_%) to be expanded to $(foo_var1) and
subsequently replaced by a_var1.o

Please let me know whether this is possible.

Thanks,
Nalin

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