I am having fun with a makefile for latex files. For a file foo.tex,
the dependencies (figures, style files, etc) are stored in a file
foo.tex-d, whose contents are of the form:
latexdeps= ... list of files ...
In my makefile I have
-insert foo.tex-d
to load the dependencies and then below
%.dvi: %.tex $(latexdeps)
$(latex) ...
for compilation and finally, I also have
%.tex-d: %.log
latexdeps ...
which will re-create the dependency file upon my explicit request.
So, currently my make file is generic as far as compilation goes, but
I have to hard-code the file that has to be -include-d. In the
example above, I am including foo.tex-d, but all my other rules have
wildcards. If I want to compile a different file, I have to change
the makefile -include commands to point to the new file.
Is there some way of doing the inclusion via wildcards? Or shall I
call make via a script that will assign a variable when calling make,
and then use that variable in the -include command?
I'm new to make and compilation on unix.
Thanks
Mirko Vukovic
Tokyo Electron Arizona
Gilbert Arizona
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