Re[2]: can't compute prerequisites in static pattern rule

[Evgeny Sologubov]

Hello, Noel,
Tuesday, December 16, 2003, 5:02:03 PM, You wrote:
>>[...]
NY> For example, in the end, I think what you want is to generate
NY> a dependency file for a project.  The usual way to do this is to
NY> include that dependency file within the makefile.  This inclusion
NY> cannot be done generically, but this really shouldn't be a
NY> problem since, presumably, you should know what project
NY> you're trying to build, anyway.  Is this not so?

Assume that I have four projects situated in four folders: .\Main,
.\Lib1, .\Lib2 and .\Lib3
Where
1. Main depends on Lib1
2. Lib1 depends on Lib2 and Lib3
3. Lib2 depends on Lib3

As you can see project Main doesn't know a bit about projects Lib2 and Lib3.
I wanted to create such universal rule to recursively build "Main" and
all of the Libs it (directly or indirectly) depends on:

all: prj-Main
prj-%: $(addprefix prj-, $(shell cat -s %/Makefile.dep))
       $(MAKE) -C $*

where files %/Makefile.dep contain names of prerequisites.
E.g. Lib1/Makefile.dep = "Lib2 Lib3".

It comes to mind only 2 ways how I can rewrite it:
1. Just place all the knowledge about dependencies into my main Makefile.
So it will look like that:
all: Main
Main: Lib1
      $(MAKE) -C $@
....
Lib17: Lib15 Lib13 ... Lib1
       $(MAKE) -C $@

2. Makefile of every project must invoke making of all the Libs it
depends on.

I believe that 2nd way better than 1st because of "incapsulation" of
prerequisites info. But there is some problem with it - making of Lib3
will be invoked twice (by Lib1 and by Lib2) and that could cause
noticeable time penalties (especially when number of Libs much greater
than 3)!

I'd appreciate any ideas about ways to solve that problem.
thanks in advance.

-- 
Evgeny

P.S. Sorry for my English :(