Makefile template and dependency problem

[Roland Schuld]

Hi,

I am trying to create a makefile construct consisting of three files.
Makefile.common contains all the global variable definitions like CC, 
CXX, LD ...
Makefile.rules conains all the rules (implicit and explicit) that will 
be called by an object or target to be created.
Makefile is the only one file the user has to edit to build his project. 
It contains the variables for the source files the headers and other 
includes and defines also the targetname to be built.

These are the files:

Makefile.common --------------------------------------------------------

# MAKEFILE *************************************************************
#
# Project:      Build Automation
# Filename:     Makefile
#
#       (C) Copyright 2005 Roland Schuld
#
# Author:       Roland Schuld
#
# $Id$
# **********************************************************************

# default mode for compiling
# changed externally by passing mode=release to make
mode=debug

CC=gcc

CXX=g++

CCE=gcc -E

CXXE=g++ -E

CFLAGS_debug=

CFLAGS_release=-funroll-all-loops #-pedantic

CXXFLAGS_debug=-g

LDFLAGS_debug=-lm

CXXFLAGS_release=-funroll-all-loops -O3 #-pedantic

LDFLAGS_release=-lm

CXXFLAGS_optimize=-funroll-loops -O2 #-pedantic

LDFLAGS_optimize=-lm

DEFAULTFLAGS=-Wall -c -I.

CFLAGS=$(DEFAULTFLAGS) $(CFLAGS_$(mode))

CXXFLAGS=$(DEFAULTFLAGS) -Wno-deprecated $(CXXFLAGS_$(mode))

LDFLAGS=$(LDFLAGS_$(mode))

ARFLAGS=-rcs

EXTRAFLAGS=

BACKUPDIR=backup/$(shell date +%Y-%m-%d)

Makefile.rules ---------------------------------------------------------

# MAKEFILE *************************************************************
#
# Project: Build Automation
# Filename: Makefile.rules
#
#      (C) Copyright 2005 Roland Schuld
# Author: Roland Schuld
#
# $Id$
# **********************************************************************

# Define a fictive target for checking if we got an executable
EXECUTABLE=NO_TARGET_DEFINED

# Check if we got an executable
# If so, define the target
ifeq ($(suffix $(TARGET)),)
    EXECUTABLE=$(TARGET)
endif


TARGETDIR := ../objects
TARGET := $(addprefix $(TARGETDIR)/, $(TARGET))


TOBJECTS := $(addsuffix .o, $(basename $(SOURCES)))
TOBJECTS := $(addprefix $(TARGETDIR)/, $(TOBJECTS))


# phony targets
.PHONY : all clean lessclean cleandir mrproper depend backup $(DIRS)

# currently supported suffixes
# clean up suffixes and set again
.SUFFIXES :
.SUFFIXES : .o .c .cc .cpp .a .l

all: $(TARGET) $(DIRS)

# explicit rules to use

$(EXECUTABLE): $(TOBJECTS)
        $(CXX) $(TOBJECTS) $(LDFLAGS) -o $@

################################################################################
#                       IMPLICIT RULES
################################################################################

$(TARGETDIR)/%.o: %.cc %.h
        @if ! test -d $(TARGETDIR); then mkdir $(TARGETDIR); fi
        $(CXX) $(CXXFLAGS) -o $@ $<

$(TARGETDIR)/%.o : %.c %.h
        @if ! test -d $(TARGETDIR); then mkdir $(TARGETDIR); fi
        $(CC) $(CFLAGS) -o $@ $<

$(TARGETDIR)/%.o : %.cpp %.h
        @if ! test -d $(TARGETDIR); then mkdir $(TARGETDIR); fi
        $(CXX) $(CXXFLAGS) -o $@ $<

%.c : %.l
        $(LEX) $(LFLAGS) $<

$(TARGETDIR)/%.a : $(TOBJECTS)
        $(AR) $(ARFLAGS) $(TARGET) $(TOBJECTS)

$(TARGETDIR)/%.so : $(TOBJECTS)
        $(CXX) $(LDFLAGS) -shared -o $(TARGET) $(TOBJECTS)

# **********************************************************************
#                                 PHONY TARGETS
# **********************************************************************

$(DIRS):
        cd $@ && $(MAKE)

clean:
ifneq ($(strip $(TARGET)),)
        $(RM) $(TARGET) $(TOBJECTS) *~ *.o
else
        $(foreach dir,$(DIRS),$(MAKE) -C $(dir) clean;)
endif

lessclean:
ifneq ($(strip $(TARGET)),)
        $(RM) $(TARGET) $(TOBJECTS)
else
        $(foreach dir,$(DIRS),$(MAKE) -C $(dir) lessclean;)
endif

cleandir:
        $(RM) *~

mrproper:
ifneq ($(strip $(TARGET)),)
        $(RM) -r $(TARGETDIR) *~ .depend
else
        $(foreach dir,$(DIRS),$(MAKE) -C $(dir) mrproper;)
endif

depend:
        $(CCE) -MM $(SOURCES) -I. > .depend

backup:
        @if test ! -d backup; then mkdir backup; fi
        @if test ! -d $(BACKUPDIR); then mkdir $(BACKUPDIR); fi
        cp -f $(SOURCES) $(HEADERS) $(INCLUDES) Makefile $(BACKUPDIR)

Makefile ---------------------------------------------------------------

# MAKEFILE *************************************************************
#
# Project:
# Filename:   Makefile
#
#       (C) Copyright 2005 Roland Schuld
#
# Author:     Roland Schuld
# Created:
#
# $Id$
# **********************************************************************

include Makefile.common

SOURCES:=

HEADERS:=

INCLUDES:=

TARGET:=

include Makefile.rules

--------------------------------------------------------------------------------

Now I ran into a problem with the dependencies. I defined a PHONY target 
"depend" which will create a file ".depend" containing all the 
prerequisites depending directly to the files. But I am not sure how to 
make the sourcefiles depend on it. If I try to compile something that 
has a header called equal to the name of the source file, there is no 
problem (of course, cause the rule tells so). But it is impossible to 
compile a source file that has no header called like itself.

So how can I make make extracting the dependencies from the dependency 
file and adding it to the rule on-the-fly?

Any suggestion will be appreciated.

Thanks in advance Roland Schuld