Does a variable contain the Makefile's name?

[Karl Itschen]

Hello
I have a makefile called "Makefile-original"
In this file, I would like to make a target choosing between two different 
compilers (and corresponding options)

I call it to compile with g++ using 
$make -f Makefile-original g++
or 
$make -f Makefile-original icc
(to compile with icc)

The file looks like this

--makefile--
<snip lots of stuff>
MAKEFILE = Makefile-original

g++:
        $(MAKE) -f $(MAKEFILE) all CC="$(GPP)" CFLAGS="$(GCFLAGS)" LD="$(GPLD)" 
LDFLAGS="$(GLDFLAGS)" LIBS="$(GLIBS)" PROG="$(GPROG)"

icc:
        $(MAKE) -f $(MAKEFILE) all CC="$(ICC)" CFLAGS="$(ICFLAGS)" LD="$(ILD)" 
LDFLAGS="$(ILDFLAGS)" LIBS="$(ILIBS)" PROG="$(IPROG)"

<snip other stuff>
----

Now as you see, I call "make" inside the makefile using $(MAKE) and the 
makefile name is passed in as -f $(MAKEFILE). But this has to be hand set in 
the makefile. If I change the name of the makefile, it doesn't work anymore (or 
needs editing to point to the new makefile name).

So my question is: Is there a variable which contains the name of the makefile 
(in shell you would have something like $0 or $1 automatically containing 
arguments to the call)?
If not: Is there a more beautiful way to achieve the same result, ie compiling 
with different compilers specified at command line?

Thanks for your answers
Karl