Re: makefile parsing and variable expansion

[Paul Smith]

On Wed, 2009-09-30 at 21:47 +0100, Ian Lynagh wrote:
> I am trying to understand how makefiles are parsed, e.g. why this
> makefile:
> # -----------
> default:
>       echo hello
> define foo
> q:
>       echo this is q1
>       echo this is q2
> endef
> $(foo)
> # -----------
> 
> ends up containing this (according to "make -pr"):
> 
> # -----------
> q: echo this is q1
>  echo this is q2
> # -----------

Because make's parser is line-based.  Each logical line that is read
from the makefile is considered a single line EVEN IF, after expansion,
it contains newlines.  A variable statement like this CANNOT expand into
a construct that spans multiple logical lines.

If you want to do that, you'll need to use $(eval ...) (which you can
read about in the GNU make manual):

        $(eval $(foo))

will do what you want.

> I am also confused as to why the above Makefile is accepted, while:
> 
> # -----------
> default:
>       echo hello
> 
> q: echo this is q1
>  echo this is q2
> # -----------

Because make, as above, is line-based.  There's no _normal_ way to
introduce a newline into a filename in a prerequisite list.  The only
way to do it is via define/endef as you've done.

Actually, this is probably a bug in the make parser; it should throw out
newlines in prerequisite lists... or anyway treat them like any other
whitespace.  Is there a valid use-case for supporting filenames
containing newlines?

-- 
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 Paul D. Smith <address@hidden>          Find some GNU make tips at:
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