Re: help with converting /usr/ccs/bin/make to GNU make

[Paul Smith]

On Fri, 2010-07-23 at 13:52 -0400, Polder, Matthew J wrote:
> #This is the part that doesn’t work. I’ve tried $^, $< but they
> resolve to blank space instead of
> #the desired name of the cpp file.
> 
> $(OBJS): $(patsubst %.o,%.cpp,$(notdir $@))
>             g++ -c $^ -o $@
> 
> #I used to use this line
> #${OBJS}: address@hidden:%.o=%.cpp}
> #          g++ -c ${*F}.cpp -o $@

You can't do that because make (even Solaris make) resolves the contents
of prerequisite lists when the makefile is read in, and at that time
automatic variables like $@ are not set (they are only set much later,
when make tries to run the rule).  That's why, in Solaris make, you have
to escape the "$" in the prerequisites list.

See the GNU make manual, in particular the section "How make Reads a
Makefile".

For this particular translation you can use static pattern rules, like
this:

        $(OBJS) : %.o : %.c
                g++ -c $< -o $@

(you shouldn't be using $^, that expands to ALL the prerequisites which
you definitely do not want).  See the GNU make manual for details, but
it should be pretty obvious from the syntax.

In your translation you added a $(notdir ...).  The Sun version you show
doesn't do that and neither does my example above.  If you really want
that then you'll have to get a lot trickier.


You can do more or less what the Solaris makefile does, and even more
actually, but you have to enable secondary expansion (see the GNU make
manual for an explanation).