Re: Recompile files for different parameters

[Krzysztof Cieniuch]

Matthias Fechner wrote:
> On 08.03.11 11:09, Krzysztof Cieniuch wrote:
> > Had the same problem and someone pointed me to linux kernel Makefile 
> > system
> > they have solution for that. In short when you build object file (as
> > well as any other target type) you should record
> > in dependency file, command line that was used to build that target and
> > then force build if command changed.
> > Search archives for mail  "Detecting Makefile changes in incremental
> > builds"
>
> thanks for that tip it seems to be exactly what I need.
> I played around with some combinations but I just started to write 
> Makefiles, so it is very hard to really understand how it works.
>
> What I did now is:
> 1. I added into the .c.o target two new commands to generate a .d file 
> with all dependencies and a line to create the new .cmd file with the 
> script fixdep from the linux kernel source
>
> 2. I added a line to include the .cmd files into the make process.
>
> But what is not clear for me, how can I say make to rebuild if the 
> command line changed?
> If I understood it correctly I must create a reference to the target 
> cmd_$<: but I have not really an idea how to do this.
>
> Attach the current Makefile.
>
> Thanks,
> Matthias
>
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The first problem with your makefile is that you cannot use automatic 
variable  ($@) in prerequisite list unless you turn on
second expansion (I don't use that feature so do not know much about it 
but use in sample below :-))).
Makefile system I wrote is very explicit i.e. every rule is explicitly 
stated (actually generated I heavily rely on eval and call)
I never use pattern rules so don't know how my approach would work here 
but anyways I've put working example:

you will need following:
file.h:
//can be empty
file.c:
#include <stdio.h>
#include "file.h"
int main(int argc,char* argv[]){
return 0;
}

Makefile:
#include generated dependency makefile (do not fail if doesn't exists to 
make first time build)
-include file.d
#turn on second expansion
.SECONDEXPANSION:

CC:=gcc
CFLAGS:=-O3
CPPFLAGS:=
WARN_FLAGS:=-Wall

#space character can be used in subst
_sp:=
_sp+=

.PHONY: FORCE

#compute current command arguments "checksum" :-) need to remove spaces 
so checksum check below using filter-out function is going to work
cmdargs:=$(subst $(_sp),,$(CC) $(CFLAGS) $(CPPFLAGS) $(WARN_FLAGS))

#rebuild file.o if file.c changed or command arguments checksum changed
file.o: file.c $$(if $$(filter-out $$(cmdargs_$$(@)),$$(cmdargs)),FORCE)
   @$(CC) -M $(CPPFLAGS) -o $(basename $(@)).d $<
   @ echo 'cmdargs_$(@):=$(cmdargs)' >> $(basename $(@)).d
   $(CC) -c $(CFLAGS) $(CPPFLAGS) $(WARN_FLAGS) -o $@ $<

Note about above rule:
first line generates dependency file without actually compiling anything

second line appends (instead of creating another file) command 
"checksum" info to generated dependency file i.e. file.d.

and the third is compilation.

now if you change any *FLAGS variable it should recompile file.o
Hope this will help at least will give you starting point.

Chris