Re: Makefile error

[Paul Smith]

On Fri, 2011-04-15 at 08:34 +0200, Dapp, Eric (E F IE TI 2) wrote:
> 
> makefile:162: *** prerequisites cannot be defined in command scripts. Stop.
> 
> Am i doing something wrong ?

A number of things, I think.

First, inside your "define RULES" you are creating a number of rules but
none of your recipes contain the required leading TAB character:

> define RULES
> ...
> $(1): $$(ASM_OBJECTS_$(1)) $$(C_OBJECTS_$(1))
> $(CC) $(LDFLAGS) -T"$(AT91LIB)/boards/$(BOARD)/$(CHIP)/address@hidden" -o

This line (and all other recipe lines)  must begin with TAB like any
other rule.

Second, and this is probably where the error comes from, you've indented
your foreach loop with a TAB although this is intended to be makefile
syntax, not a recipe:

>       $(foreach MEMORY, $(MEMORIES), $(eval $(call RULES,$(MEMORY))))

There should not be a TAB at the beginning of this line.

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