[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
Re: Append dependencies through variables
From: |
Riccardo Manfrin |
Subject: |
Re: Append dependencies through variables |
Date: |
Sun, 26 May 2013 19:49:37 +0200 |
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:17.0) Gecko/20130308 Thunderbird/17.0.4 |
On 05/26/2013 01:00 AM, Paul Smith wrote:
Your example works for me. Are you sure you used EXACTLY this example
to reproduce the problem? I'll bet you had something like this instead:
all: $(MAKE_DEPS_ALL)
@echo $(MAKE_DEPS_ALL)
include Makefile1
You are absolutely right, I actually had my includes *after* the "all:"
target, in order to have the make process find the "all" target before
the others.
Rule targets and prerequisites are expanded immediately when the
makefile is parsed, so changes to variables after they appear in targets
and prerequisites are not reflected there.
Ok, so is there a way to force a prerequisite to be expanded *after* the
variable it is made of has been evaluated throughout the whole makefile?
I've been reading the documentation and aldready tried with
".SECONDEXPANSION" but could not find the proper way to use it.
In this particular case, though, you don't need to create a variable.
Just add the prerequisite as you go:
all: mydep
mydep:
$(MAKE) -C /my/path
Let me depict the scenario. My project is made by some software modules
that I optionally include or not in the compile process. I'd like to
keep the main Makefile very simple and have those module Makefiles
dictate the all prerequisites dependencies. This way the description of
the prerequisites is scattered but the main Makefile does not need to be
aware of what software modules to compile.
I can go with your solution and that would be oK, but I'd like to
understand if there is a way to force prerequisite expansion after
variable evaluation.
Thanks in advance,
R