[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
Re: Sandy Bridge
From: |
Sergei Steshenko |
Subject: |
Re: Sandy Bridge |
Date: |
Sun, 21 Oct 2012 17:43:48 -0700 (PDT) |
----- Original Message -----
> From: Martin Helm <address@hidden>
> To: Graaf_van_Vlaanderen <address@hidden>; "address@hidden" <address@hidden>
> Cc:
> Sent: Monday, October 22, 2012 2:05 AM
> Subject: Re: Sandy Bridge
>
> If and when your CPU steps to a different speed has absolutely nothing
> to do with how a program is compiled, it solely depends on the settings
> of the CPU governor in your operating system.
>
I am not sure that the situation is that straightforward.
For example, it is known that RAM accesses are much slower than cache ones. And
if the CPU HW sees too many RAM accesses it may not speed up the CPU - it will
still be waiting for data from RAM.
If OTOH there are a lot of cache accesses, it makes for the CPU sense to work
faster.
Cache <-> RAM may be dependent on compiler optimizations - compilers are often
aware of cache friendliness.
And, specifically, ATLAS is built in cache friendliness awareness mode.
Regards,
Sergei.