[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-arm] [RFC PATCH v2 10/12] Convert zynq's slcr to 3-phases reset
From: |
Damien Hedde |
Subject: |
[Qemu-arm] [RFC PATCH v2 10/12] Convert zynq's slcr to 3-phases reset |
Date: |
Tue, 4 Jun 2019 18:25:24 +0200 |
Change the legacy reset function into the init phase and test the
resetting flag in register accesses.
Signed-off-by: Damien Hedde <address@hidden>
---
hw/misc/zynq_slcr.c | 39 +++++++++++++++++++++++++++++++++++----
1 file changed, 35 insertions(+), 4 deletions(-)
diff --git a/hw/misc/zynq_slcr.c b/hw/misc/zynq_slcr.c
index baa13d1316..c6d2bba966 100644
--- a/hw/misc/zynq_slcr.c
+++ b/hw/misc/zynq_slcr.c
@@ -171,6 +171,17 @@ REG32(DDRIOB, 0xb40)
#define TYPE_ZYNQ_SLCR "xilinx,zynq_slcr"
#define ZYNQ_SLCR(obj) OBJECT_CHECK(ZynqSLCRState, (obj), TYPE_ZYNQ_SLCR)
+#define ZYNQ_SLCR_CLASS(class) \
+ OBJECT_CLASS_CHECK(ZynqSLCRClass, (class), TYPE_ZYNQ_SLCR)
+#define ZYNQ_SLCR_GET_CLASS(obj) \
+ OBJECT_GET_CLASS(ZynqSLCRClass, (obj), TYPE_ZYNQ_SLCR)
+
+typedef struct ZynqSLCRClass {
+ /*< private >*/
+ SysBusDeviceClass parent_class;
+
+ struct ResettablePhases parent_reset_phases;
+} ZynqSLCRClass;
typedef struct ZynqSLCRState {
SysBusDevice parent_obj;
@@ -180,13 +191,18 @@ typedef struct ZynqSLCRState {
uint32_t regs[ZYNQ_SLCR_NUM_REGS];
} ZynqSLCRState;
-static void zynq_slcr_reset(DeviceState *d)
+static void zynq_slcr_reset_init(Object *obj, bool cold)
{
- ZynqSLCRState *s = ZYNQ_SLCR(d);
+ ZynqSLCRState *s = ZYNQ_SLCR(obj);
+ ZynqSLCRClass *zc = ZYNQ_SLCR_GET_CLASS(obj);
int i;
DB_PRINT("RESET\n");
+ if (zc->parent_reset_phases.init) {
+ zc->parent_reset_phases.init(obj, cold);
+ }
+
s->regs[R_LOCKSTA] = 1;
/* 0x100 - 0x11C */
s->regs[R_ARM_PLL_CTRL] = 0x0001A008;
@@ -276,7 +292,6 @@ static void zynq_slcr_reset(DeviceState *d)
s->regs[R_DDRIOB + 12] = 0x00000021;
}
-
static bool zynq_slcr_check_offset(hwaddr offset, bool rnw)
{
switch (offset) {
@@ -346,6 +361,10 @@ static uint64_t zynq_slcr_read(void *opaque, hwaddr offset,
offset /= 4;
uint32_t ret = s->regs[offset];
+ if (device_is_resetting((DeviceState *) opaque)) {
+ return 0;
+ }
+
if (!zynq_slcr_check_offset(offset, true)) {
qemu_log_mask(LOG_GUEST_ERROR, "zynq_slcr: Invalid read access to "
" addr %" HWADDR_PRIx "\n", offset * 4);
@@ -361,6 +380,10 @@ static void zynq_slcr_write(void *opaque, hwaddr offset,
ZynqSLCRState *s = (ZynqSLCRState *)opaque;
offset /= 4;
+ if (device_is_resetting((DeviceState *) opaque)) {
+ return;
+ }
+
DB_PRINT("addr: %08" HWADDR_PRIx " data: %08" PRIx64 "\n", offset * 4,
val);
if (!zynq_slcr_check_offset(offset, false)) {
@@ -439,9 +462,16 @@ static const VMStateDescription vmstate_zynq_slcr = {
static void zynq_slcr_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
+ ResettableClass *rc = RESETTABLE_CLASS(klass);
+ ZynqSLCRClass *zc = ZYNQ_SLCR_CLASS(klass);
dc->vmsd = &vmstate_zynq_slcr;
- dc->reset = zynq_slcr_reset;
+
+ resettable_class_set_parent_reset_phases(rc,
+ zynq_slcr_reset_init,
+ NULL,
+ NULL,
+ &zc->parent_reset_phases);
}
static const TypeInfo zynq_slcr_info = {
@@ -450,6 +480,7 @@ static const TypeInfo zynq_slcr_info = {
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(ZynqSLCRState),
.instance_init = zynq_slcr_init,
+ .class_size = sizeof(ZynqSLCRClass),
};
static void zynq_slcr_register_types(void)
--
2.21.0
- [Qemu-arm] [RFC PATCH v2 00/12] Multi-phase reset, Damien Hedde, 2019/06/04
- [Qemu-arm] [RFC PATCH v2 02/12] add device_legacy_reset function to do the transition with device_reset, Damien Hedde, 2019/06/04
- [Qemu-arm] [RFC PATCH v2 03/12] replace all occurences of device_reset by device_legacy_reset, Damien Hedde, 2019/06/04
- [Qemu-arm] [RFC PATCH v2 01/12] Create Resettable QOM interface, Damien Hedde, 2019/06/04
- [Qemu-arm] [RFC PATCH v2 05/12] Add function to control reset with gpio inputs, Damien Hedde, 2019/06/04
- [Qemu-arm] [RFC PATCH v2 06/12] add vmstate description for device reset state, Damien Hedde, 2019/06/04
- [Qemu-arm] [RFC PATCH v2 04/12] make Device and Bus Resettable, Damien Hedde, 2019/06/04
- [Qemu-arm] [RFC PATCH v2 07/12] add doc about Resettable interface, Damien Hedde, 2019/06/04
- [Qemu-arm] [RFC PATCH v2 09/12] convert cadence_uart to 3-phases reset, Damien Hedde, 2019/06/04
- [Qemu-arm] [RFC PATCH v2 10/12] Convert zynq's slcr to 3-phases reset,
Damien Hedde <=
- [Qemu-arm] [RFC PATCH v2 08/12] hw/misc/zynq_slcr: use standard register definition, Damien Hedde, 2019/06/04
- [Qemu-arm] [RFC PATCH v2 11/12] Add uart reset support in zynq_slcr, Damien Hedde, 2019/06/04
- [Qemu-arm] [RFC PATCH v2 12/12] Connect the uart reset gpios in the zynq platform, Damien Hedde, 2019/06/04
- Re: [Qemu-arm] [RFC PATCH v2 00/12] Multi-phase reset, Peter Maydell, 2019/06/18