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Re: [Qemu-arm] [PATCH 16/42] target/arm: Convert the VFP load/store mult
From: |
Richard Henderson |
Subject: |
Re: [Qemu-arm] [PATCH 16/42] target/arm: Convert the VFP load/store multiple insns to decodetree |
Date: |
Sat, 8 Jun 2019 09:04:13 -0500 |
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.7.0 |
On 6/6/19 12:45 PM, Peter Maydell wrote:
> Convert the VFP load/store multiple insns to decodetree.
> This includes tightening up the UNDEF checking for pre-VFPv3
> CPUs which only have D0-D15 : they now UNDEF for any access
> to D16-D31, not merely when the smallest register in the
> transfer list is in D16-D31.
>
> This conversion does not try to share code between the single
> precision and the double precision versions; this looks a bit
> duplicative of code, but it leaves the door open for a future
> refactoring which gets rid of the use of the "F0" registers
> by inlining the various functions like gen_vfp_ld() and
> gen_mov_F0_reg() which are hiding "if (dp) { ... } else { ... }"
> conditionalisation.
>
> Signed-off-by: Peter Maydell <address@hidden>
> ---
> target/arm/translate-vfp.inc.c | 162 +++++++++++++++++++++++++++++++++
> target/arm/translate.c | 97 +-------------------
> target/arm/vfp.decode | 18 ++++
> 3 files changed, 183 insertions(+), 94 deletions(-)
Reviewed-by: Richard Henderson <address@hidden>
r~
- Re: [Qemu-arm] [PATCH 09/42] target/arm: Convert VCVTA/VCVTN/VCVTP/VCVTM to decodetree, (continued)
- [Qemu-arm] [PATCH 05/42] target/arm: Explicitly enable VFP short-vectors for aarch32 -cpu max, Peter Maydell, 2019/06/06
- [Qemu-arm] [PATCH 39/42] target/arm: Convert VJCVT to decodetree, Peter Maydell, 2019/06/06
- [Qemu-arm] [PATCH 22/42] target/arm: Convert VMUL to decodetree, Peter Maydell, 2019/06/06
- [Qemu-arm] [PATCH 08/42] target/arm: Convert VRINTA/VRINTN/VRINTP/VRINTM to decodetree, Peter Maydell, 2019/06/06
- [Qemu-arm] [PATCH 16/42] target/arm: Convert the VFP load/store multiple insns to decodetree, Peter Maydell, 2019/06/06
- Re: [Qemu-arm] [PATCH 16/42] target/arm: Convert the VFP load/store multiple insns to decodetree,
Richard Henderson <=
- [Qemu-arm] [PATCH 17/42] target/arm: Remove VLDR/VSTR/VLDM/VSTM use of cpu_F0s and cpu_F0d, Peter Maydell, 2019/06/06
- [Qemu-arm] [PATCH 13/42] target/arm: Convert "single-precision" register moves to decodetree, Peter Maydell, 2019/06/06
- [Qemu-arm] [PATCH 11/42] target/arm: Add helpers for VFP register loads and stores, Peter Maydell, 2019/06/06
- [Qemu-arm] [PATCH 34/42] target/arm: Convert the VCVT-from-f16 insns to decodetree, Peter Maydell, 2019/06/06
- [Qemu-arm] [PATCH 42/42] target/arm: Fix short-vector increment behaviour, Peter Maydell, 2019/06/06