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[Qemu-arm] [PATCH v2 05/42] target/arm: Explicitly enable VFP short-vect
From: |
Peter Maydell |
Subject: |
[Qemu-arm] [PATCH v2 05/42] target/arm: Explicitly enable VFP short-vectors for aarch32 -cpu max |
Date: |
Tue, 11 Jun 2019 11:53:14 +0100 |
At the moment our -cpu max for AArch32 supports VFP short-vectors
because we always implement them, even for CPUs which should
not have them. The following commits are going to switch to
using the correct ID-register-check to enable or disable short
vector support, so we need to turn it on explicitly for -cpu max,
because Cortex-A15 doesn't implement it.
We don't enable this for the AArch64 -cpu max, because the v8A
architecture never supports short-vectors.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
---
target/arm/cpu.c | 4 ++++
1 file changed, 4 insertions(+)
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index ac5adb81bf1..cdd76c54444 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -2021,6 +2021,10 @@ static void arm_max_initfn(Object *obj)
kvm_arm_set_cpu_features_from_host(cpu);
} else {
cortex_a15_initfn(obj);
+
+ /* old-style VFP short-vector support */
+ cpu->isar.mvfr0 = FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1);
+
#ifdef CONFIG_USER_ONLY
/* We don't set these in system emulation mode for the moment,
* since we don't correctly set (all of) the ID registers to
--
2.20.1
- [Qemu-arm] [PATCH v2 00/42] target/arm: Convert VFP decoder to decodetree, Peter Maydell, 2019/06/11
- [Qemu-arm] [PATCH v2 04/42] target/arm: Fix Cortex-R5F MVFR values, Peter Maydell, 2019/06/11
- [Qemu-arm] [PATCH v2 02/42] target/arm: Add stubs for AArch32 VFP decodetree, Peter Maydell, 2019/06/11
- [Qemu-arm] [PATCH v2 03/42] target/arm: Factor out VFP access checking code, Peter Maydell, 2019/06/11
- [Qemu-arm] [PATCH v2 09/42] target/arm: Convert VCVTA/VCVTN/VCVTP/VCVTM to decodetree, Peter Maydell, 2019/06/11
- [Qemu-arm] [PATCH v2 06/42] target/arm: Convert the VSEL instructions to decodetree, Peter Maydell, 2019/06/11
- [Qemu-arm] [PATCH v2 14/42] target/arm: Convert VFP two-register transfer insns to decodetree, Peter Maydell, 2019/06/11
- [Qemu-arm] [PATCH v2 05/42] target/arm: Explicitly enable VFP short-vectors for aarch32 -cpu max,
Peter Maydell <=
- [Qemu-arm] [PATCH v2 11/42] target/arm: Add helpers for VFP register loads and stores, Peter Maydell, 2019/06/11
- [Qemu-arm] [PATCH v2 13/42] target/arm: Convert "single-precision" register moves to decodetree, Peter Maydell, 2019/06/11
- [Qemu-arm] [PATCH v2 12/42] target/arm: Convert "double-precision" register moves to decodetree, Peter Maydell, 2019/06/11
- [Qemu-arm] [PATCH v2 07/42] target/arm: Convert VMINNM, VMAXNM to decodetree, Peter Maydell, 2019/06/11
- [Qemu-arm] [PATCH v2 01/42] decodetree: Fix comparison of Field, Peter Maydell, 2019/06/11
- [Qemu-arm] [PATCH v2 08/42] target/arm: Convert VRINTA/VRINTN/VRINTP/VRINTM to decodetree, Peter Maydell, 2019/06/11
- [Qemu-arm] [PATCH v2 15/42] target/arm: Convert VFP VLDR and VSTR to decodetree, Peter Maydell, 2019/06/11
- [Qemu-arm] [PATCH v2 17/42] target/arm: Remove VLDR/VSTR/VLDM/VSTM use of cpu_F0s and cpu_F0d, Peter Maydell, 2019/06/11
- [Qemu-arm] [PATCH v2 10/42] target/arm: Move the VFP trans_* functions to translate-vfp.inc.c, Peter Maydell, 2019/06/11
- [Qemu-arm] [PATCH v2 22/42] target/arm: Convert VMUL to decodetree, Peter Maydell, 2019/06/11