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Re: [Qemu-arm] [PATCH v2 08/21] aspeed/timer: Status register contains r


From: Joel Stanley
Subject: Re: [Qemu-arm] [PATCH v2 08/21] aspeed/timer: Status register contains reload for stopped timer
Date: Wed, 19 Jun 2019 02:12:38 +0000

On Tue, 18 Jun 2019 at 16:54, Cédric Le Goater <address@hidden> wrote:
>
> From: Andrew Jeffery <address@hidden>
>
> From the datasheet:
>
>   This register stores the current status of counter #N. When timer
>   enable bit TMC30[N * b] is disabled, the reload register will be
>   loaded into this counter. When timer bit TMC30[N * b] is set, the
>   counter will start to decrement. CPU can update this register value
>   when enable bit is set.
>
> Signed-off-by: Andrew Jeffery <address@hidden>
> Signed-off-by: Cédric Le Goater <address@hidden>

Reviewed-by: Joel Stanley <address@hidden>



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