[Qemu-arm] [RFC PATCH 6/7] misc: CCIX endpoint function

[Jonathan Cameron]

This handles the case where a given function is not also a
PCIe topology upstream or downstream port.

This include, non function 0 functions on upstream ports and
any function on a device without a PCIe switch.  Note that
this doesn't exclude the possibility of this being the upstream
port of a CCIX layer switch.

Signed-off-by: Jonathan Cameron <address@hidden>
---
 hw/misc/Kconfig       |   5 ++
 hw/misc/Makefile.objs |   1 +
 hw/misc/ccix-ep.c     | 112 ++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 118 insertions(+)

diff --git a/hw/misc/Kconfig b/hw/misc/Kconfig
index 385e1b0cec..7aba167999 100644
--- a/hw/misc/Kconfig
+++ b/hw/misc/Kconfig
@@ -118,3 +118,8 @@ config AUX
     select I2C
 
 source macio/Kconfig
+
+config CCIX_EP
+    bool
+    select CCIX_LIB
+    
\ No newline at end of file
diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs
index 77b9df9796..56a6cb3591 100644
--- a/hw/misc/Makefile.objs
+++ b/hw/misc/Makefile.objs
@@ -6,6 +6,7 @@ common-obj-$(CONFIG_ISA_DEBUG) += debugexit.o
 common-obj-$(CONFIG_SGA) += sga.o
 common-obj-$(CONFIG_ISA_TESTDEV) += pc-testdev.o
 common-obj-$(CONFIG_PCI_TESTDEV) += pci-testdev.o
+common-obj-$(CONFIG_CCIX_EP) += ccix-ep.o
 common-obj-$(CONFIG_EDU) += edu.o
 common-obj-$(CONFIG_PCA9552) += pca9552.o
 
diff --git a/hw/misc/ccix-ep.c b/hw/misc/ccix-ep.c
new file mode 100644
index 0000000000..40a5b22dd8
--- /dev/null
+++ b/hw/misc/ccix-ep.c
@@ -0,0 +1,112 @@
+/*
+ * CCIX EP configuration space test device
+ *
+ * Copyright (c) 2019 Huawei
+ * Author: Jonathan Cameron <address@hidden>
+ *
+ * Portions copied from pci-testdev.c
+ * Copyright (c) 2012 Red Hat Inc.
+ * Author: Michael S. Tsirkin <address@hidden>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+#include "qemu/osdep.h"
+#include "hw/hw.h"
+#include "hw/pci/pci.h"
+#include "qemu/event_notifier.h"
+#include "sysemu/kvm.h"
+#include "hw/misc/ccix.h"
+#include "qemu/module.h"
+
+typedef struct CCIXEpState {
+    PCIDevice parent_obj;
+    struct CCIXState s;
+
+} CCIXEpState;
+
+#define TYPE_CCIX_EP "ccix-ep"
+#define CCIX_EP_DEV(obj) OBJECT_CHECK(CCIXEpState, (obj), TYPE_CCIX_EP)
+
+static void ccix_ep_write_config(PCIDevice *pci_dev, uint32_t addr,
+                                 uint32_t val_in, int l)
+{
+    CCIXEpState *s = CCIX_EP_DEV(pci_dev);
+
+    ccix_write_config(pci_dev, &s->s, addr, val_in, l); 
+    pci_default_write_config(pci_dev, addr, val_in, l);
+}
+
+static void ccix_ep_realize(PCIDevice *pci_dev, Error **errp)
+{
+    CCIXEpState *s = CCIX_EP_DEV(pci_dev);
+    int offset = PCI_CONFIG_SPACE_SIZE;
+
+    if (PCI_FUNC(pci_dev->devfn) == 0)
+        ccix_set_port(&s->s);
+    initialize_ccixstate(&s->s, pci_dev);
+    pci_dev->config_write = ccix_ep_write_config;
+    pcie_endpoint_cap_init(pci_dev, 0);
+    offset = ccix_add_prldvsec(pci_dev, &s->s, offset);
+    if (s->s.flags & (1 << CCIX_IS_PORT))
+        ccix_add_tdldvsec(pci_dev, offset);
+
+    pci_dev->config[PCI_INTERRUPT_PIN] = 0; /* no interrupt pin */
+    ccix_register(&s->s);
+}
+
+static Property ccix_props[] = {
+    DEFINE_PROP_STRING("ccix_device", CCIXEpState, s.ccix_dev_name),
+    DEFINE_PROP_BIT("primaryport", CCIXEpState, s.flags, PRIMARY_PORT_BIT, 
true),
+    DEFINE_PROP_UINT8("port_id", CCIXEpState, s.port_id, 0),
+    DEFINE_PROP_UINT8("num_links", CCIXEpState, s.num_links, 1),
+    DEFINE_PROP_UINT8("psam_entries", CCIXEpState, s.psam_entries, 0),
+    DEFINE_PROP_UINT8("request_agents", CCIXEpState, s.num_ras, 0),
+    DEFINE_PROP_UINT8("home_agents", CCIXEpState, s.num_has, 0),
+    DEFINE_PROP_UINT8("hsam_entries", CCIXEpState, s.hsam_entries, 0),
+    DEFINE_PROP_UINT8("rsam_entries", CCIXEpState, s.rsam_entries, 0),
+    DEFINE_PROP_END_OF_LIST(),
+};
+
+static void ccix_ep_class_init(ObjectClass *klass, void *data)
+{
+    DeviceClass *dc = DEVICE_CLASS(klass);
+    PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
+
+    k->realize = ccix_ep_realize;
+    k->vendor_id = PCI_VENDOR_ID_HUAWEI;
+    k->device_id = PCI_DEVICE_ID_HUAWEI_CCIX_EP;
+    k->revision = 0x00;
+    k->class_id = PCI_CLASS_OTHERS;
+    dc->desc = "CCIX EP Test Device";
+    set_bit(DEVICE_CATEGORY_MISC, dc->categories);
+    dc->props = ccix_props;
+}
+
+static const TypeInfo ccix_ep_info = {
+    .name          = TYPE_CCIX_EP,
+    .parent        = TYPE_PCI_DEVICE,
+    .instance_size = sizeof(CCIXEpState),
+    .class_init    = ccix_ep_class_init,
+    .interfaces = (InterfaceInfo[]) {
+        { INTERFACE_PCIE_DEVICE },
+        { },
+    },
+};
+
+static void ccix_register_types(void)
+{
+    type_register_static(&ccix_ep_info);
+}
+
+type_init(ccix_register_types)
-- 
2.20.1