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Re: [Qemu-arm] [PATCH 10/67] target/arm: Move test for AL into arm_skip_
From: |
Peter Maydell |
Subject: |
Re: [Qemu-arm] [PATCH 10/67] target/arm: Move test for AL into arm_skip_unless |
Date: |
Mon, 29 Jul 2019 15:32:36 +0100 |
On Fri, 26 Jul 2019 at 18:50, Richard Henderson
<address@hidden> wrote:
>
> We will shortly be calling this function much more often.
>
> Signed-off-by: Richard Henderson <address@hidden>
> ---
> target/arm/translate.c | 28 ++++++++++++----------------
> 1 file changed, 12 insertions(+), 16 deletions(-)
>
> diff --git a/target/arm/translate.c b/target/arm/translate.c
> index 53c46fcdc4..36419025db 100644
> --- a/target/arm/translate.c
> +++ b/target/arm/translate.c
> @@ -7705,8 +7705,14 @@ static void arm_gen_condlabel(DisasContext *s)
> /* Skip this instruction if the ARM condition is false */
> static void arm_skip_unless(DisasContext *s, uint32_t cond)
> {
> - arm_gen_condlabel(s);
> - arm_gen_test_cc(cond ^ 1, s->condlabel);
> + /*
> + * Conditionally skip the insn. Note that both 0xe and 0xf mean
> + * "always"; 0xf is not "never".
> + */
> + if (cond < 0xe) {
> + arm_gen_condlabel(s);
> + arm_gen_test_cc(cond ^ 1, s->condlabel);
> + }
> }
>
> static void disas_arm_insn(DisasContext *s, unsigned int insn)
> @@ -7944,11 +7950,9 @@ static void disas_arm_insn(DisasContext *s, unsigned
> int insn)
> }
> goto illegal_op;
> }
> - if (cond != 0xe) {
> - /* if not always execute, we generate a conditional jump to
> - next instruction */
> - arm_skip_unless(s, cond);
> - }
> +
> + arm_skip_unless(s, cond);
> +
> if ((insn & 0x0f900000) == 0x03000000) {
> if ((insn & (1 << 21)) == 0) {
> ARCH(6T2);
> @@ -12095,15 +12099,7 @@ static void thumb_tr_translate_insn(DisasContextBase
> *dcbase, CPUState *cpu)
> dc->insn = insn;
>
> if (dc->condexec_mask && !thumb_insn_is_unconditional(dc, insn)) {
> - uint32_t cond = dc->condexec_cond;
> -
> - /*
> - * Conditionally skip the insn. Note that both 0xe and 0xf mean
> - * "always"; 0xf is not "never".
> - */
> - if (cond < 0x0e) {
> - arm_skip_unless(dc, cond);
> - }
> + arm_skip_unless(dc, dc->condexec_cond);
> }
In the other callsites for arm_skip_unless() the cond argument
can never be 0xe or 0xf.
Reviewed-by: Peter Maydell <address@hidden>
thanks
-- PMM
- [Qemu-arm] [PATCH 09/67] target/arm: Fold a pc load into load_reg, (continued)
- [Qemu-arm] [PATCH 09/67] target/arm: Fold a pc load into load_reg, Richard Henderson, 2019/07/26
- [Qemu-arm] [PATCH 07/67] target/arm: Introduce add_reg_for_lit, Richard Henderson, 2019/07/26
- [Qemu-arm] [PATCH 12/67] target/arm: Introduce gen_illegal_op, Richard Henderson, 2019/07/26
- [Qemu-arm] [PATCH 11/67] target/arm: Add stubs for aa32 decodetree, Richard Henderson, 2019/07/26
- [Qemu-arm] [PATCH 10/67] target/arm: Move test for AL into arm_skip_unless, Richard Henderson, 2019/07/26
- Re: [Qemu-arm] [PATCH 10/67] target/arm: Move test for AL into arm_skip_unless,
Peter Maydell <=
- [Qemu-arm] [PATCH 15/67] target/arm: Convert Saturating addition and subtraction, Richard Henderson, 2019/07/26
- [Qemu-arm] [PATCH 16/67] target/arm: Convert Halfword multiply and multiply accumulate, Richard Henderson, 2019/07/26
- [Qemu-arm] [PATCH 14/67] target/arm: Convert multiply and multiply accumulate, Richard Henderson, 2019/07/26
- [Qemu-arm] [PATCH 17/67] target/arm: Convert MSR (immediate) and hints, Richard Henderson, 2019/07/26
- [Qemu-arm] [PATCH 20/67] target/arm: Convert the rest of A32 Miscelaneous instructions, Richard Henderson, 2019/07/26
- [Qemu-arm] [PATCH 18/67] target/arm: Convert MRS/MSR (banked, register), Richard Henderson, 2019/07/26
- [Qemu-arm] [PATCH 21/67] target/arm: Convert T32 ADDW/SUBW, Richard Henderson, 2019/07/26
- [Qemu-arm] [PATCH 13/67] target/arm: Convert Data Processing (reg, reg-shifted-reg, imm), Richard Henderson, 2019/07/26