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[PATCH v3 09/16] hw/arm/bcm2836: Create VideoCore address space in the S
From: |
Philippe Mathieu-Daudé |
Subject: |
[PATCH v3 09/16] hw/arm/bcm2836: Create VideoCore address space in the SoC |
Date: |
Sun, 20 Oct 2019 01:47:08 +0200 |
Currently the VideoCore is created in the Peripheral container
as the 'GPU bus'. It is created there because the peripherals
using DMA use physical addresses from the VideoCore bus.
However the VideoCore is a GPU core placed at the same
hierarchical level than the ARM cores.
To match the datasheet design, create the VideoCore container
in the SoC, and link it to the peripheral container.
The VideoCore bus is 1GiB wide, accessible at 4 regions in
different cache configurations. Add the full mapping.
Before this commit the memory tree is:
(qemu) info mtree
address-space: bcm2835-dma-memory
0000000000000000-00000000ffffffff (prio 0, i/o): bcm2835-gpu
0000000000000000-000000003fffffff (prio 0, i/o): alias
bcm2835-gpu-ram-alias[*] @ram 0000000000000000-000000003fffffff
0000000040000000-000000007fffffff (prio 0, i/o): alias
bcm2835-gpu-ram-alias[*] @ram 0000000000000000-000000003fffffff
000000007e000000-000000007effffff (prio 1, i/o): alias
bcm2835-peripherals @bcm2835-peripherals 0000000000000000-0000000000ffffff
0000000080000000-00000000bfffffff (prio 0, i/o): alias
bcm2835-gpu-ram-alias[*] @ram 0000000000000000-000000003fffffff
00000000c0000000-00000000ffffffff (prio 0, i/o): alias
bcm2835-gpu-ram-alias[*] @ram 0000000000000000-000000003fffffff
After:
address-space: bcm2835-dma-memory
0000000000000000-00000000ffffffff (prio 0, i/o): gpu-bus
0000000000000000-000000003fffffff (prio 0, i/o): alias l1-l2-cached
@videocore 0000000000000000-000000003fffffff
0000000040000000-000000007fffffff (prio 0, i/o): alias l2-cached-coherent
@videocore 0000000000000000-000000003fffffff
0000000080000000-00000000bfffffff (prio 0, i/o): alias l2-cached
@videocore 0000000000000000-000000003fffffff
00000000c0000000-00000000ffffffff (prio 0, i/o): alias direct-uncached
@videocore 0000000000000000-000000003fffffff
memory-region: videocore
0000000000000000-000000003fffffff (prio 0, i/o): videocore
0000000000000000-000000003fffffff (prio 0, i/o): alias vc-ram @ram
0000000000000000-000000003fffffff
000000003e000000-000000003effffff (prio 1, i/o): alias vc-peripherals
@bcm2835-peripherals 0000000000000000-0000000000ffffff
Now the periferals are accessible from the uncached region too.
Signed-off-by: Philippe Mathieu-Daudé <address@hidden>
---
hw/arm/bcm2835_peripherals.c | 25 +++++-------------
hw/arm/bcm2836.c | 38 ++++++++++++++++++++++++++++
include/hw/arm/bcm2835_peripherals.h | 4 +--
include/hw/arm/bcm2836.h | 7 +++++
4 files changed, 53 insertions(+), 21 deletions(-)
diff --git a/hw/arm/bcm2835_peripherals.c b/hw/arm/bcm2835_peripherals.c
index d51e9c8def..5da310efb1 100644
--- a/hw/arm/bcm2835_peripherals.c
+++ b/hw/arm/bcm2835_peripherals.c
@@ -9,6 +9,7 @@
*/
#include "qemu/osdep.h"
+#include "qemu/units.h"
#include "qapi/error.h"
#include "qemu/module.h"
#include "hw/arm/bcm2835_peripherals.h"
@@ -45,10 +46,6 @@ static void bcm2835_peripherals_init(Object *obj)
object_property_add_child(obj, "peripheral-io", OBJECT(&s->peri_mr), NULL);
sysbus_init_mmio(SYS_BUS_DEVICE(s), &s->peri_mr);
- /* Internal memory region for peripheral bus addresses (not exported) */
- memory_region_init(&s->gpu_bus_mr, obj, "bcm2835-gpu", (uint64_t)1 << 32);
- object_property_add_child(obj, "gpu-bus", OBJECT(&s->gpu_bus_mr), NULL);
-
/* Internal memory region for request/response communication with
* mailbox-addressable peripherals (not exported)
*/
@@ -140,21 +137,11 @@ static void bcm2835_peripherals_realize(DeviceState *dev,
Error **errp)
ram = MEMORY_REGION(obj);
ram_size = memory_region_size(ram);
- /* Map peripherals and RAM into the GPU address space. */
- memory_region_init_alias(&s->peri_mr_alias, OBJECT(s),
- "bcm2835-peripherals", &s->peri_mr, 0,
- memory_region_size(&s->peri_mr));
-
- memory_region_add_subregion_overlap(&s->gpu_bus_mr, BCM2835_VC_PERI_BASE,
- &s->peri_mr_alias, 1);
-
- obj = OBJECT(&s->gpu_bus_mr);
- /* RAM is aliased four times (different cache configurations) on the GPU */
- for (n = 0; n < 4; n++) {
- memory_region_init_alias(&s->ram_alias[n], OBJECT(s),
- "bcm2835-gpu-ram-alias[*]", ram, 0, ram_size);
- memory_region_add_subregion_overlap(&s->gpu_bus_mr, (hwaddr)n << 30,
- &s->ram_alias[n], 0);
+ obj = object_property_get_link(OBJECT(dev), "videocore-bus", &err);
+ if (obj == NULL) {
+ error_setg(errp, "%s: required videocore-bus link not found: %s",
+ __func__, error_get_pretty(err));
+ return;
}
/* Interrupt Controller */
diff --git a/hw/arm/bcm2836.c b/hw/arm/bcm2836.c
index 374a44b38c..ada35e5620 100644
--- a/hw/arm/bcm2836.c
+++ b/hw/arm/bcm2836.c
@@ -51,6 +51,14 @@ static void bcm2836_init(Object *obj)
const BCM283XInfo *info = bc->info;
int n;
+ /* VideoCore memory region */
+ memory_region_init(&s->vc.gpu, obj, "videocore", 1 * GiB);
+ object_property_add_child(obj, "videocore", OBJECT(&s->vc.gpu), NULL);
+
+ /* Internal memory region for peripheral bus addresses (not exported) */
+ memory_region_init(&s->vc.bus, obj, "gpu-bus", 4 * GiB);
+ object_property_add_child(obj, "gpu-bus", OBJECT(&s->vc.bus), NULL);
+
for (n = 0; n < BCM283X_NCPUS; n++) {
memory_region_init(&s->cpu[n].container, obj, "cpu-bus", 4 * GiB);
@@ -97,6 +105,12 @@ static void bcm2836_realize(DeviceState *dev, Error **errp)
error_propagate(errp, err);
return;
}
+ object_property_add_const_link(OBJECT(&s->peripherals), "videocore-bus",
+ OBJECT(&s->vc.bus), &err);
+ if (err) {
+ error_propagate(errp, err);
+ return;
+ }
object_property_set_bool(OBJECT(&s->peripherals), true, "realized", &err);
if (err) {
error_propagate(errp, err);
@@ -112,6 +126,30 @@ static void bcm2836_realize(DeviceState *dev, Error **errp)
peri_mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->peripherals), 0);
+ /* Map peripherals and RAM into the GPU address space. */
+ memory_region_init_alias(&s->vc.peri_alias, OBJECT(s),
+ "vc-peripherals", peri_mr, 0,
+ memory_region_size(peri_mr));
+ memory_region_add_subregion_overlap(&s->vc.gpu, 0x3e000000,
+ &s->vc.peri_alias, 1);
+ memory_region_init_alias(&s->vc.ram_alias, OBJECT(s),
+ "vc-ram", ram_mr, 0, ram_size);
+ memory_region_add_subregion(&s->vc.gpu, 0,
+ &s->vc.ram_alias);
+ static const char * const bus_alias_name[] = {
+ "l1-l2-cached",
+ "l2-cached-coherent",
+ "l2-cached",
+ "direct-uncached"
+ };
+ /* Alias different cache configurations on the GPU */
+ for (n = 0; n < ARRAY_SIZE(bus_alias_name); n++) {
+ memory_region_init_alias(&s->vc.gpu_alias[n], OBJECT(s),
+ bus_alias_name[n], &s->vc.gpu, 0, 1 * GiB);
+ memory_region_add_subregion(&s->vc.bus, n * GiB,
+ &s->vc.gpu_alias[n]);
+ }
+
/* bcm2836 interrupt controller (and mailboxes, etc.) */
object_property_set_bool(OBJECT(&s->control), true, "realized", &err);
if (err) {
diff --git a/include/hw/arm/bcm2835_peripherals.h
b/include/hw/arm/bcm2835_peripherals.h
index 7859281e11..fb6d84ec50 100644
--- a/include/hw/arm/bcm2835_peripherals.h
+++ b/include/hw/arm/bcm2835_peripherals.h
@@ -36,8 +36,8 @@ typedef struct BCM2835PeripheralState {
SysBusDevice parent_obj;
/*< public >*/
- MemoryRegion peri_mr, peri_mr_alias, gpu_bus_mr, mbox_mr;
- MemoryRegion ram_alias[4];
+ MemoryRegion peri_mr, mbox_mr;
+
qemu_irq irq, fiq;
BCM2835SystemTimerState systmr;
diff --git a/include/hw/arm/bcm2836.h b/include/hw/arm/bcm2836.h
index e3498cb861..787ab76738 100644
--- a/include/hw/arm/bcm2836.h
+++ b/include/hw/arm/bcm2836.h
@@ -35,6 +35,13 @@ typedef struct BCM283XState {
char *cpu_type;
uint32_t enabled_cpus;
+ struct {
+ MemoryRegion bus;
+ MemoryRegion gpu;
+ MemoryRegion peri_alias;
+ MemoryRegion ram_alias;
+ MemoryRegion gpu_alias[4];
+ } vc;
struct {
ARMCPU core;
MemoryRegion container;
--
2.21.0
- Re: [PATCH v3 03/16] hw/timer/bcm2835: Add the BCM2835 SYS_timer, (continued)
- [PATCH v3 05/16] hw/arm/bcm2836: Make the SoC code modular, Philippe Mathieu-Daudé, 2019/10/19
- [PATCH v3 06/16] hw/arm/bcm2836: Rename cpus[] as cpu[].core, Philippe Mathieu-Daudé, 2019/10/19
- [PATCH v3 08/16] hw/arm/bcm2835_peripherals: Add const link property in realize(), Philippe Mathieu-Daudé, 2019/10/19
- [PATCH v3 07/16] hw/arm/bcm2836: Use per CPU address spaces, Philippe Mathieu-Daudé, 2019/10/19
- [PATCH v3 09/16] hw/arm/bcm2836: Create VideoCore address space in the SoC,
Philippe Mathieu-Daudé <=
- [PATCH v3 10/16] hw/arm/raspi: Use AddressSpace when using arm_boot::write_secondary_boot, Philippe Mathieu-Daudé, 2019/10/19
- [PATCH v3 11/16] hw/arm/raspi: Use -smp cores=<N> option to restrict enabled cores, Philippe Mathieu-Daudé, 2019/10/19
- [PATCH v3 12/16] hw/arm/bcm2836: Rename enabled_cpus -> enabled_cores, Philippe Mathieu-Daudé, 2019/10/19
- [PATCH v3 13/16] hw/arm/raspi: Make the board code modular, Philippe Mathieu-Daudé, 2019/10/19
- [PATCH v3 15/16] python/qemu/machine: Allow to use other serial consoles than default, Philippe Mathieu-Daudé, 2019/10/19
- [PATCH v3 14/16] hw/arm/highbank: Use AddressSpace when using write_secondary_boot(), Philippe Mathieu-Daudé, 2019/10/19