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[PATCH v3 11/42] target/arm: Reorg regime_translation_disabled
From: |
Richard Henderson |
Subject: |
[PATCH v3 11/42] target/arm: Reorg regime_translation_disabled |
Date: |
Sat, 1 Oct 2022 09:22:47 -0700 |
Use a switch on mmu_idx for the a-profile indexes, instead of
three different if's vs regime_el and arm_mmu_idx_is_stage1_of_2.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/arm/ptw.c | 32 +++++++++++++++++++++++++-------
1 file changed, 25 insertions(+), 7 deletions(-)
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
index 9be11f1673..2875ea881c 100644
--- a/target/arm/ptw.c
+++ b/target/arm/ptw.c
@@ -148,21 +148,39 @@ static bool regime_translation_disabled(CPUARMState *env,
ARMMMUIdx mmu_idx,
hcr_el2 = arm_hcr_el2_eff(env);
- if (mmu_idx == ARMMMUIdx_Stage2 || mmu_idx == ARMMMUIdx_Stage2_S) {
+ switch (mmu_idx) {
+ case ARMMMUIdx_Stage2:
+ case ARMMMUIdx_Stage2_S:
/* HCR.DC means HCR.VM behaves as 1 */
return (hcr_el2 & (HCR_DC | HCR_VM)) == 0;
- }
- if (hcr_el2 & HCR_TGE) {
+ case ARMMMUIdx_E10_0:
+ case ARMMMUIdx_E10_1:
+ case ARMMMUIdx_E10_1_PAN:
/* TGE means that NS EL0/1 act as if SCTLR_EL1.M is zero */
- if (!is_secure && regime_el(env, mmu_idx) == 1) {
+ if (!is_secure && (hcr_el2 & HCR_TGE)) {
return true;
}
- }
+ break;
- if ((hcr_el2 & HCR_DC) && arm_mmu_idx_is_stage1_of_2(mmu_idx)) {
+ case ARMMMUIdx_Stage1_E0:
+ case ARMMMUIdx_Stage1_E1:
+ case ARMMMUIdx_Stage1_E1_PAN:
/* HCR.DC means SCTLR_EL1.M behaves as 0 */
- return true;
+ if (hcr_el2 & HCR_DC) {
+ return true;
+ }
+ break;
+
+ case ARMMMUIdx_E20_0:
+ case ARMMMUIdx_E20_2:
+ case ARMMMUIdx_E20_2_PAN:
+ case ARMMMUIdx_E2:
+ case ARMMMUIdx_E3:
+ break;
+
+ default:
+ g_assert_not_reached();
}
return (regime_sctlr(env, mmu_idx) & SCTLR_M) == 0;
--
2.34.1
- Re: [PATCH v3 01/42] target/arm: Split s2walk_secure from ipa_secure in get_phys_addr, (continued)
[PATCH v3 02/42] target/arm: Add is_secure parameter to get_phys_addr_lpae, Richard Henderson, 2022/10/01
[PATCH v3 03/42] target/arm: Fix S2 disabled check in S1_ptw_translate, Richard Henderson, 2022/10/01
[PATCH v3 04/42] target/arm: Add is_secure parameter to regime_translation_disabled, Richard Henderson, 2022/10/01
[PATCH v3 05/42] target/arm: Split out get_phys_addr_with_secure, Richard Henderson, 2022/10/01
[PATCH v3 06/42] target/arm: Add is_secure parameter to v7m_read_half_insn, Richard Henderson, 2022/10/01
[PATCH v3 13/42] target/arm: Introduce arm_hcr_el2_eff_secstate, Richard Henderson, 2022/10/01
[PATCH v3 10/42] target/arm: Fold secure and non-secure a-profile mmu indexes, Richard Henderson, 2022/10/01
[PATCH v3 11/42] target/arm: Reorg regime_translation_disabled,
Richard Henderson <=
[PATCH v3 15/42] target/arm: Remove env argument from combined_attrs_fwb, Richard Henderson, 2022/10/01
[PATCH v3 12/42] target/arm: Drop secure check for HCR.TGE vs SCTLR_EL1.M, Richard Henderson, 2022/10/01
[PATCH v3 14/42] target/arm: Hoist read of *is_secure in S1_ptw_translate, Richard Henderson, 2022/10/01
[PATCH v3 16/42] target/arm: Pass HCR to attribute subroutines., Richard Henderson, 2022/10/01
[PATCH v3 07/42] target/arm: Add TBFLAG_M32.SECURE, Richard Henderson, 2022/10/01
[PATCH v3 08/42] target/arm: Merge regime_is_secure into get_phys_addr, Richard Henderson, 2022/10/01
[PATCH v3 19/42] target/arm: Fix cacheattr in get_phys_addr_disabled, Richard Henderson, 2022/10/01
[PATCH v3 20/42] target/arm: Use tlb_set_page_full, Richard Henderson, 2022/10/01