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Re: [PATCH v2 1/5] Refactor i.MX6UL processor code


From: Philippe Mathieu-Daudé
Subject: Re: [PATCH v2 1/5] Refactor i.MX6UL processor code
Date: Mon, 31 Jul 2023 16:31:05 +0200
User-agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.15; rv:102.0) Gecko/20100101 Thunderbird/102.13.0

Hi Jean-Christophe,

On 29/7/23 23:17, Jean-Christophe Dubois wrote:
* Add Addr and size definition for all i.MX6UL devices in i.MX6UL header file.
* Use those newly defined named constants whenever possible.
* Standardize the way we init a familly of unimplemented devices
   - SAI
   - PWM (add missing PWM instances)
   - CAN
* Add/rework few comments

Signed-off-by: Jean-Christophe Dubois <jcd@tribudubois.net>
---
  hw/arm/fsl-imx6ul.c         | 149 ++++++++++++++++++++++++------------
  include/hw/arm/fsl-imx6ul.h | 149 +++++++++++++++++++++++++++++++++---
  2 files changed, 239 insertions(+), 59 deletions(-)


  enum FslIMX6ULMemoryMap {
      FSL_IMX6UL_MMDC_ADDR            = 0x80000000,
-    FSL_IMX6UL_MMDC_SIZE            = 2 * 1024 * 1024 * 1024UL,
+    FSL_IMX6UL_MMDC_SIZE            = (2 * 1024 * 1024 * 1024UL),
FSL_IMX6UL_QSPI1_MEM_ADDR = 0x60000000,
+    FSL_IMX6UL_QSPI1_MEM_SIZE       = (256 * 1024 * 1024UL),
+
      FSL_IMX6UL_EIM_ALIAS_ADDR       = 0x58000000,
+    FSL_IMX6UL_EIM_ALIAS_SIZE       = (128 * 1024 * 1024UL),
+
      FSL_IMX6UL_EIM_CS_ADDR          = 0x50000000,
+    FSL_IMX6UL_EIM_CS_SIZE          = (128 * 1024 * 1024UL),
+
      FSL_IMX6UL_AES_ENCRYPT_ADDR     = 0x10000000,
+    FSL_IMX6UL_AES_ENCRYPT_SIZE     = (1024 * 1024UL),
+
      FSL_IMX6UL_QSPI1_RX_ADDR        = 0x0C000000,
+    FSL_IMX6UL_QSPI1_RX_SIZE        = (32 * 1024 * 1024UL),

Please use the KiB / MiB definitions from "qemu/units.h" (the
resulting code is easier to read. No need for parenthesis.



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