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[RFC Patch 3/5] hw/display: Allwinner A10 Display Engine Backend emulati
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From: |
Strahinja Jankovic |
|
Subject: |
[RFC Patch 3/5] hw/display: Allwinner A10 Display Engine Backend emulation |
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Date: |
Tue, 5 Sep 2023 22:14:23 +0200 |
This patch adds Display Engine Backend 0 (DEBE0) support.
This peripheral will hold runtime configuration for the display size and
framebuffer offset which will be used by other components.
Signed-off-by: Strahinja Jankovic <strahinja.p.jankovic@gmail.com>
---
hw/arm/allwinner-a10.c | 9 +
hw/display/allwinner-a10-debe.c | 229 ++++++++++++++++++++++++
hw/display/meson.build | 3 +-
hw/display/trace-events | 4 +
include/hw/arm/allwinner-a10.h | 2 +
include/hw/display/allwinner-a10-debe.h | 71 ++++++++
6 files changed, 317 insertions(+), 1 deletion(-)
create mode 100644 hw/display/allwinner-a10-debe.c
create mode 100644 include/hw/display/allwinner-a10-debe.h
diff --git a/hw/arm/allwinner-a10.c b/hw/arm/allwinner-a10.c
index 75cd879d24..624e95af46 100644
--- a/hw/arm/allwinner-a10.c
+++ b/hw/arm/allwinner-a10.c
@@ -43,6 +43,7 @@
#define AW_A10_I2C0_BASE 0x01c2ac00
#define AW_A10_HDMI_BASE 0x01c16000
#define AW_A10_GPU_BASE 0x01c40000
+#define AW_A10_DE_BE0_BASE 0x01e60000
void allwinner_a10_bootrom_setup(AwA10State *s, BlockBackend *blk)
{
@@ -100,6 +101,8 @@ static void aw_a10_init(Object *obj)
object_initialize_child(obj, "hdmi", &s->hdmi, TYPE_AW_A10_HDMI);
+ object_initialize_child(obj, "de_be0", &s->de_be0, TYPE_AW_A10_DEBE);
+
object_initialize_child(obj, "mali400", &s->gpu, TYPE_AW_GPU);
}
@@ -221,6 +224,12 @@ static void aw_a10_realize(DeviceState *dev, Error **errp)
sysbus_realize(SYS_BUS_DEVICE(&s->hdmi), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->hdmi), 0, AW_A10_HDMI_BASE);
+ /* Display Engine Backend */
+ object_property_set_uint(OBJECT(&s->de_be0), "ram-base",
+ AW_A10_SDRAM_BASE, &error_fatal);
+ sysbus_realize(SYS_BUS_DEVICE(&s->de_be0), &error_fatal);
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->de_be0), 0, AW_A10_DE_BE0_BASE);
+
/* MALI GPU */
sysbus_realize(SYS_BUS_DEVICE(&s->gpu), &error_fatal);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpu), 0, AW_A10_GPU_BASE);
diff --git a/hw/display/allwinner-a10-debe.c b/hw/display/allwinner-a10-debe.c
new file mode 100644
index 0000000000..3760728eab
--- /dev/null
+++ b/hw/display/allwinner-a10-debe.c
@@ -0,0 +1,229 @@
+/*
+ * Allwinner A10 Display Engine Backend emulation
+ *
+ * Copyright (C) 2023 Strahinja Jankovic <strahinja.p.jankovic@gmail.com>
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/units.h"
+#include "hw/sysbus.h"
+#include "migration/vmstate.h"
+#include "qemu/log.h"
+#include "qemu/module.h"
+#include "hw/qdev-properties.h"
+#include "hw/display/allwinner-a10-debe.h"
+#include "trace.h"
+
+/* DEBE register offsets - only important ones */
+enum {
+ REG_DEBE_MODCTL = 0x0800, /* DE mode control */
+ REG_DEBE_DISSIZE = 0x0808, /* DE display size */
+ REG_DEBE_LAY0FB_L32ADD = 0x0850, /* DE Layer 0 lower 32-bit address */
+ REG_DEBE_REGBUFFCTL = 0x0870, /* DE buffer control register */
+ REG_DEBE_ATTCTL_REG1_L0 = 0x08A0, /* DE Layer 0 attribute ctrl reg 1 */
+};
+
+/* DEBE_DISSIZE fields */
+#define FIELD_DEBE_DISSIZE_DIS_HEIGHT (16)
+#define FIELD_DEBE_DISSIZE_DIS_WIDTH (0)
+#define DEBE_DISSIZE_DIS_MASK (0xFFFFu)
+
+/* DEBE_REGBUFFCTL fields */
+#define FIELD_DEBE_REGBUFFCTL_REGLOADCTL (1)
+#define FIELD_DEBE_REGBUFFCTL_REGAUTOLOAD_DIS (2)
+
+/* DEBE_ATTCTL_REG1_L0 fields */
+#define FIELD_DEBE_ATTCTL_REG1_L0_LAY_FBFMT (8)
+#define DEBE_ATTCTL_REG1_L0_LAY_FBFMT_MASK (0xFu)
+enum {
+ ATTCTL_REG1_LAY_FBFMT_MONO_1BPP = 0,
+ ATTCTL_REG1_LAY_FBFMT_MONO_2BPP,
+ ATTCTL_REG1_LAY_FBFMT_MONO_4BPP,
+ ATTCTL_REG1_LAY_FBFMT_MONO_8BPP,
+ ATTCTL_REG1_LAY_FBFMT_COLOR_16BPP_655,
+ ATTCTL_REG1_LAY_FBFMT_COLOR_16BPP_565,
+ ATTCTL_REG1_LAY_FBFMT_COLOR_16BPP_556,
+ ATTCTL_REG1_LAY_FBFMT_COLOR_16BPP_1555,
+ ATTCTL_REG1_LAY_FBFMT_COLOR_16BPP_5551,
+ ATTCTL_REG1_LAY_FBFMT_COLOR_32BPP_P888,
+ ATTCTL_REG1_LAY_FBFMT_COLOR_32BPP_8888,
+ ATTCTL_REG1_LAY_FBFMT_COLOR_24BPP_888,
+ ATTCTL_REG1_LAY_FBFMT_COLOR_16BPP_4444,
+};
+
+static uint8_t debe_lay_fbfmt_bpp[] = {
+ 1,
+ 2,
+ 4,
+ 8,
+ 16,
+ 16,
+ 16,
+ 16,
+ 16,
+ 32,
+ 32,
+ 24,
+ 16
+};
+
+#define REG_INDEX(offset) (offset / sizeof(uint32_t))
+
+static uint64_t allwinner_a10_debe_read(void *opaque, hwaddr offset,
+ unsigned size)
+{
+ const AwA10DEBEState *s = AW_A10_DEBE(opaque);
+ const uint32_t idx = REG_INDEX(offset);
+ uint32_t val = 0;
+
+ switch (offset) {
+ case REG_DEBE_DISSIZE:
+ case REG_DEBE_LAY0FB_L32ADD:
+ case REG_DEBE_REGBUFFCTL:
+ break;
+ case 0x5800 ... AW_A10_DEBE_IOSIZE:
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n",
+ __func__, (uint32_t)offset);
+ return 0;
+ default:
+ break;
+ }
+
+ val = s->regs[idx];
+
+ trace_allwinner_a10_debe_read(offset, val);
+
+ return val;
+}
+
+static void allwinner_a10_debe_write(void *opaque, hwaddr offset,
+ uint64_t val, unsigned size)
+{
+ AwA10DEBEState *s = AW_A10_DEBE(opaque);
+ const uint32_t idx = REG_INDEX(offset);
+
+ trace_allwinner_a10_debe_write(offset, (uint32_t)val);
+
+ switch (offset) {
+ case REG_DEBE_DISSIZE:
+ /* Store display width and height */
+ s->height = 1 +
+ ((val >> FIELD_DEBE_DISSIZE_DIS_HEIGHT) & DEBE_DISSIZE_DIS_MASK);
+ s->width = 1 +
+ ((val >> FIELD_DEBE_DISSIZE_DIS_WIDTH) & DEBE_DISSIZE_DIS_MASK);
+ s->invalidate = true;
+ break;
+ case REG_DEBE_LAY0FB_L32ADD:
+ /* Store framebuffer offset */
+ s->framebuffer_offset = s->ram_base + (val >> 3);
+ if (val != 0) {
+ s->ready = true;
+ }
+ break;
+ case REG_DEBE_REGBUFFCTL:
+ if (val ==
+ (FIELD_DEBE_REGBUFFCTL_REGLOADCTL |
+ FIELD_DEBE_REGBUFFCTL_REGAUTOLOAD_DIS)) {
+ /* Clear to indicate that register loading is done. */
+ val &= ~FIELD_DEBE_REGBUFFCTL_REGLOADCTL;
+ }
+ break;
+ case REG_DEBE_ATTCTL_REG1_L0:
+ {
+ uint8_t bpp = (val >> FIELD_DEBE_ATTCTL_REG1_L0_LAY_FBFMT) &
+ DEBE_ATTCTL_REG1_L0_LAY_FBFMT_MASK;
+ s->bpp = debe_lay_fbfmt_bpp[bpp];
+ }
+ break;
+ case 0x5800 ... AW_A10_DEBE_IOSIZE:
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: out-of-bounds offset 0x%04x\n",
+ __func__, (uint32_t)offset);
+ break;
+ default:
+ break;
+ }
+
+ s->regs[idx] = (uint32_t) val;
+}
+
+static const MemoryRegionOps allwinner_a10_debe_ops = {
+ .read = allwinner_a10_debe_read,
+ .write = allwinner_a10_debe_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
+ .valid = {
+ .min_access_size = 4,
+ .max_access_size = 4,
+ },
+ .impl.min_access_size = 4,
+};
+
+static void allwinner_a10_debe_reset_enter(Object *obj, ResetType type)
+{
+ AwA10DEBEState *s = AW_A10_DEBE(obj);
+
+ memset(&s->regs[0], 0, AW_A10_DEBE_IOSIZE);
+}
+
+static void allwinner_a10_debe_init(Object *obj)
+{
+ SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
+ AwA10DEBEState *s = AW_A10_DEBE(obj);
+
+ /* Memory mapping */
+ memory_region_init_io(&s->iomem, OBJECT(s), &allwinner_a10_debe_ops, s,
+ TYPE_AW_A10_DEBE, AW_A10_DEBE_IOSIZE);
+ sysbus_init_mmio(sbd, &s->iomem);
+}
+
+static const VMStateDescription allwinner_a10_debe_vmstate = {
+ .name = "allwinner-a10-debe",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINT32_ARRAY(regs, AwA10DEBEState, AW_A10_DEBE_REGS_NUM),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
+static Property allwinner_a10_debe_properties[] = {
+ DEFINE_PROP_UINT64("ram-base", AwA10DEBEState, ram_base, 0),
+ DEFINE_PROP_END_OF_LIST(),
+};
+
+static void allwinner_a10_debe_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+ ResettableClass *rc = RESETTABLE_CLASS(klass);
+
+ rc->phases.enter = allwinner_a10_debe_reset_enter;
+ dc->vmsd = &allwinner_a10_debe_vmstate;
+ device_class_set_props(dc, allwinner_a10_debe_properties);
+}
+
+static const TypeInfo allwinner_a10_debe_info = {
+ .name = TYPE_AW_A10_DEBE,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_init = allwinner_a10_debe_init,
+ .instance_size = sizeof(AwA10DEBEState),
+ .class_init = allwinner_a10_debe_class_init,
+};
+
+static void allwinner_a10_debe_register(void)
+{
+ type_register_static(&allwinner_a10_debe_info);
+}
+
+type_init(allwinner_a10_debe_register)
diff --git a/hw/display/meson.build b/hw/display/meson.build
index a5eb01fe2b..a3ef580b1c 100644
--- a/hw/display/meson.build
+++ b/hw/display/meson.build
@@ -38,7 +38,8 @@ system_ss.add(when: 'CONFIG_NEXTCUBE', if_true:
files('next-fb.c'))
system_ss.add(when: 'CONFIG_VGA', if_true: files('vga.c'))
-system_ss.add(when: 'CONFIG_ALLWINNER_A10', if_true:
files('allwinner-a10-hdmi.c',
+system_ss.add(when: 'CONFIG_ALLWINNER_A10', if_true:
files('allwinner-a10-debe.c',
+
'allwinner-a10-hdmi.c',
'allwinner-gpu.c'))
if (config_all_devices.has_key('CONFIG_VGA_CIRRUS') or
diff --git a/hw/display/trace-events b/hw/display/trace-events
index d1c0f05e52..132b66fc81 100644
--- a/hw/display/trace-events
+++ b/hw/display/trace-events
@@ -178,6 +178,10 @@ macfb_sense_read(uint32_t value) "video sense: 0x%"PRIx32
macfb_sense_write(uint32_t value) "video sense: 0x%"PRIx32
macfb_update_mode(uint32_t width, uint32_t height, uint8_t depth) "setting
mode to width %"PRId32 " height %"PRId32 " size %d"
+# allwinner-a10-debe.c
+allwinner_a10_debe_read(uint64_t offset, uint64_t data) "Read: offset 0x%"
PRIx64 " data 0x%" PRIx64
+allwinner_a10_debe_write(uint64_t offset, uint64_t data) "Write: offset 0x%"
PRIx64 " data 0x%" PRIx64
+
# allwinner-a10-hdmi.c
allwinner_a10_hdmi_read(uint64_t offset, uint64_t data) "Read: offset 0x%"
PRIx64 " data 0x%" PRIx64
allwinner_a10_hdmi_write(uint64_t offset, uint64_t data) "Write: offset 0x%"
PRIx64 " data 0x%" PRIx64
diff --git a/include/hw/arm/allwinner-a10.h b/include/hw/arm/allwinner-a10.h
index 8109656421..2de7e402b2 100644
--- a/include/hw/arm/allwinner-a10.h
+++ b/include/hw/arm/allwinner-a10.h
@@ -12,6 +12,7 @@
#include "hw/rtc/allwinner-rtc.h"
#include "hw/misc/allwinner-a10-ccm.h"
#include "hw/misc/allwinner-a10-dramc.h"
+#include "hw/display/allwinner-a10-debe.h"
#include "hw/display/allwinner-a10-hdmi.h"
#include "hw/display/allwinner-gpu.h"
#include "hw/i2c/allwinner-i2c.h"
@@ -45,6 +46,7 @@ struct AwA10State {
AWI2CState i2c0;
AwRtcState rtc;
AwWdtState wdt;
+ AwA10DEBEState de_be0;
AwGpuState gpu;
AwA10HdmiState hdmi;
MemoryRegion sram_a;
diff --git a/include/hw/display/allwinner-a10-debe.h
b/include/hw/display/allwinner-a10-debe.h
new file mode 100644
index 0000000000..30727516bc
--- /dev/null
+++ b/include/hw/display/allwinner-a10-debe.h
@@ -0,0 +1,71 @@
+/*
+ * Allwinner A10 Display engine Backend emulation
+ *
+ * Copyright (C) 2023 Strahinja Jankovic <strahinja.p.jankovic@gmail.com>
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef HW_DISPLAY_ALLWINNER_A10_DEBE_H
+#define HW_DISPLAY_ALLWINNER_A10_DEBE_H
+
+#include "qom/object.h"
+#include "hw/sysbus.h"
+
+/**
+ * @name Constants
+ * @{
+ */
+
+/** Size of register I/O address space used by DEBE device */
+#define AW_A10_DEBE_IOSIZE (0x20000)
+
+/** Total number of known registers for DEBE */
+#define AW_A10_DEBE_REGS_NUM (AW_A10_DEBE_IOSIZE / sizeof(uint32_t))
+
+/** @} */
+
+/**
+ * @name Object model
+ * @{
+ */
+
+#define TYPE_AW_A10_DEBE "allwinner-a10-debe"
+OBJECT_DECLARE_SIMPLE_TYPE(AwA10DEBEState, AW_A10_DEBE)
+
+/** @} */
+
+/**
+ * Allwinner A10 DEBE object instance state.
+ */
+struct AwA10DEBEState {
+ /*< private >*/
+ SysBusDevice parent_obj;
+ /*< public >*/
+ uint32_t width;
+ uint32_t height;
+ hwaddr framebuffer_offset;
+ hwaddr ram_base;
+ uint8_t bpp;
+ bool ready;
+ bool invalidate;
+
+ /** Maps I/O registers in physical memory */
+ MemoryRegion iomem;
+
+ /** Array of hardware registers */
+ uint32_t regs[AW_A10_DEBE_REGS_NUM];
+};
+
+#endif /* HW_DISPLAY_ALLWINNER_A10_DEBE_H */
--
2.34.1